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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xrt86l30 single t1/e1/j1 framer/liu combo january 2008 rev. 1.0.1 general description the xrt86l30 is a single channel 1.544 mbit/s or 2.048 mbit/s ds1/e1/j1 framer and liu integrated solution featuring r 3 technology (relayless, reconfigurable, redundancy). the physical interface is optimized with internal impedance, and with the patented pad structure, the xrt86l30 provides protection from power failures and hot swapping. the xrt86l30 contains an integrated ds1/e1/j1 framer and liu which provide ds1/e1/j1 framing and error accumulation in accordance with ansi/itu_t specifications. the framer has a framing synchroniz er and transmit-receive slip buffers. the slip buffer s can be independently enabled or disabled as required and can be configured to frame to the common ds1/ e1/j1 signal formats. the framer block contains a transmit and receive t1/e1/j1 framing function. there are 3 transmit hdlc controllers which encapsulate contents of the transmit hdlc buffers into lapd message frames. there are 3 receive hdlc controllers which extract the payload content of receive lapd message frames from the incoming t1/e1/j1 data stream and write the contents into the receive hdlc buffers. the framer also contains a transmit and overhead data input port, which permits data link terminal equipment direct access to the outbound t1/e1/j1 frames. likewise, a receive overhead output data port permits data link terminal equipment direct access to the data link bits of the inbound t1/e1/j 1 frames. the xrt86l30 fully meets all of the latest t1/e1/j1 specifications: ansi t1/e1.107-1988, ansi t1/ e1.403-1999, ansi t1/e1.231-1993, ansi t1/ e1.408-1990, at&t tr 62411 (12-90) tr54016, and itu g-703, g.704, g706 and g.733, at&t pub. 43801, and ets 300 011, 300 233, jt g.703, jt g.704, jt g706, i.431. extensive test and diagnosti c functions include loop-backs, boundary scan, pseudo random bit sequence (prbs) test pattern generation, performance monitor, bit error rate (ber) meter, forced error insertion, and lapd unchannelized data payload processing according to itu-t standard q.921. applications and features (next page) f igure 1. xrt86l30 1- channel ds1 (t1/e1/j1) f ramer /liu c ombo performance monitor prbs generator & analyser hdlc/lapd controllers liu & loopback control dma interface signaling & alarms jtag wr ale_as rd rdy_dtack m p select a[11:0] d[7:0] microprocessor interface 4 3 tx serial clock rx serial clock 8khz sync osc back plane 1.544-16.384 mbit/s local pcm highway st-bus 2-frame slip buffer elastic store tx serial data in tx liu interface 2-frame slip buffer elastic store rx liu interface rx framer rx serial data out rtip rring ttip tring external data link controller tx overhead in rx overhead out xrt86l30 tx framer llb lb system (terminal) side line side 1:1 turns ratio 1:2 turns ratio memory intel/motorola p configuration, control & status monitor rxlos txon int
xrt86l30 2 single t1/e1/j1 framer/liu combo rev. 1.0.1 applications high-density t1/e1/j1 interfaces for multiplexers, switches, lan routers and digital modems sonet/sdh terminal or add/drop multiplexers (adms) t1/e1/j1 add/drop multiplexers (mux) channel service units (csus): t1/e1/j1 and fraction al t1/e1/j1 digital access cross-connect system (dacs) digital cross-connect systems (dcs) frame relay switches and access devices (frads) isdn primary rate interfaces (pra) pbxs and pcm channel bank t3 channelized access concentrators and m13 mux wireless base stations atm equipment with integrated ds1 interfaces multichannel ds1 test equipment t1/e1/j1 performance monitoring voice over packet gateways routers features full duplex ds1 tx and rx framer/liu two 512-bit (two-frame) elastic store, pcm frame sl ip buffers (fifo) on tx and rx provide up to 8.192 mhz asynchronous back plane connections with jitter and wander attenuation supports input pcm and signaling data at 1.544, 2.0 48, 4.096 and 8.192 mbits. also supports 4-channel multiplexed 12.352/16.384 (hmvip/h.100) mbit/s on t he back plane bus (with stuffed dont care bits for the other 3 channels) programmable output clocks for fractional t1/e1/j1 supports channel associated signaling (cas) supports common channel signalling (ccs) supports isdn primary rate interface (isdn pri) sig naling extracts and inserts robbed bit signaling (rbs) 3 integrated hdlc controllers for transmit and rece ive, each controller having two 96-byte buffers (bu ffer 0 / buffer 1) hdlc controllers support ss7 timeslot assignable hdlc v5.1 or v5.2 interface automatic performance report generation (pmon statu s) can be inserted into the transmit lapd interface every 1 second or for a single transmission alarm indication signal with customer installation signature (ais-ci) remote alarm indication with customer installation (rai-ci) gapped clock interface mode for transmit and receiv e. intel/motorola and power pc interfaces for configur ation, control and status monitoring parallel search algorithm for fast frame synchroniz ation wide choice of t1 framing structures: sf/d4, esf, s lc ? 96, t1dm and n-frame (non-signaling)
xrt86l30 3 rev. 1.0.1 single t1/e1/j1 framer/liu combo direct access to d and e channels for fast transmis sion of data link information prbs, qrss, and network loop code generation and de tection programmable interrupt output pin supports programmed i/o and dma modes of read-write access each framer block encodes and decodes the t1/e1/j1 frame serial data detects and forces red (sai), yellow (rai) and blue (ais) alarms detects oof, lof, los errors and cofa conditions loopbacks: local (llb) and line remote (lb) facilitates inverse multiplexing for atm performance monitor with one second polling boundary scan (ieee 1149.1) jtag test port accepts external 8khz sync reference 3.3v cmos operation with 5v tolerant inputs 128-pin lqfp package with -40 c to +85 c operation ordering information p art n umber p ackage o perating t emperature r ange XRT86L30IV 128 lqfp -40 c to +85 c
xrt86l30 i single t1/e1/j1 framer/liu combo rev. 1.0.1 list of paragraphs 1.0 pin list ...................................... ................................................... ................................................... .......4 2.0 pin descriptions .............................. ................................................... ...............................................8 3.0 microprocessor interface block ................ ................................................... .......................21 3.0.1 the microprocessor interface block signals .... ................................................... ................................ 21 3.1 intel mode programmed i/o access (asynchronous) .................................................. ................ 24 3.2 motorola mode programmed i/o access (synchronou s) ................................................ .......... 26 3.2.1 dma read/write operations .................... ................................................... ................................................... .... 28 3.3 memory mapped i/o addressing .................. ................................................... ....................................... 30 3.4 description of the control registers .......... ................................................... ............................... 31 3.4.1 register descriptions ....................... ................................................... ................................................... ............ 37 3.5 programming the line interface unit (liu sectio n) ................................................ ................... 118 3.6 the interrupt structure within the framer ..... ................................................... ....................... 138 3.6.1 configuring the interrupt system, at the framer l evel .............................................. .................... 141 4.0 general description and interface ............. ................................................... .....................144 4.1 physical interface ............................ ................................................... ................................................... 144 4.2 r3 technology (relayless / reconfigurable / red undancy) .......................................... ...... 145 4.2.1 line card redundancy ........................ ................................................... ................................................... ......... 145 4.2.2 typical redundancy schemes .................. ................................................... ................................................... 145 4.2.3 1:1 and 1+1 redundancy without relays ....... ................................................... .......................................... 145 4.2.4 transmit interface with 1:1 and 1+1 redundanc y ................................................. ................................. 145 4.2.5 receive interface with 1:1 and 1+1 redundancy ................................................... .................................. 146 4.3 power failure protection ...................... ................................................... .......................................... 147 4.4 overvoltage and overcurrent protection ........ ................................................... ..................... 147 4.5 non-intrusive monitoring ...................... ................................................... ............................................ 147 4.6 t1/e1 serial pcm interface .................... ................................................... ............................................ 148 4.7 t1/e1 fractional interface .................... ................................................... ........................................... 149 4.8 t1/e1 time slot substitution and control ...... ................................................... ............................ 150 4.9 robbed bit signaling/cas signaling ............ ................................................... .................................. 151 4.10 overhead interface ........................... ................................................... ................................................ 153 4.11 framer bypass mode ........................... ................................................... ............................................... 154 4.12 high-speed non-multiplexed interface ......... ................................................... ............................ 155 4.13 high-speed multiplexed interface ............. ................................................... ................................. 156 5.0 loopback modes of operation ................... ................................................... .........................157 5.1 liu physical interface loopback diagnostics ... ................................................... ...................... 157 5.1.1 local analog loopback ........................ ................................................... ................................................... .... 157 5.1.2 remote loopback ............................. ................................................... ................................................... ............. 157 5.1.3 digital loopback ............................. ................................................... ................................................... .............. 158 5.1.4 dual loopback ............................... ................................................... ................................................... ................ 158 5.1.5 framer remote line loopback .................. ................................................... ................................................. 15 8 5.1.6 framer payload loopback ..................... ................................................... ................................................... .. 159 5.1.7 framer local loopback ........................ ................................................... ................................................... ..... 159 6.0 hdlc controllers and lapd messages ............ ................................................... ................160 6.1 programming sequence for sending less than 96-b yte messages .................................... 16 0 6.2 programming sequence for sending large messages .................................................. ......... 160 6.3 programming sequence for receiving lapd message s ................................................. .......... 161 6.4 ss7 (signaling system number 7) for esf in ds1 only .............................................. .................. 161 6.5 ds1/e1 datalink transmission using the hdlc con trollers .......................................... ....... 162 6.6 transmit bos (bit oriented signaling) processor .................................................. ................... 162 6.6.1 description of bos ........................... ................................................... ................................................... ............. 162 6.6.2 priority codeword message ................... ................................................... ................................................... . 162 6.6.3 command and response information ............. ................................................... .......................................... 162 6.7 transmit mos (message oriented signaling) proce ssor .............................................. .......... 163 6.7.1 discussion of mos ............................ ................................................... ................................................... ............. 163 6.7.2 periodic performance report .................. ................................................... ................................................. 16 3 6.7.3 transmission-error event .................... ................................................... ................................................... .... 164 6.7.4 path and test signal identification message ... ................................................... ................................... 164 6.7.5 frame structure ............................. ................................................... ................................................... .............. 164 6.7.6 flag sequence ............................... ................................................... ................................................... ................. 164 6.7.7 address field ................................ ................................................... ................................................... .................. 165 6.7.8 address field extension bit (ea) .............. ................................................... .................................................. 1 65
xrt86l30 ii rev. 1.0.1 single t1/e1/j1 framer/liu combo 6.7.9 command or response bit (c/r) ............... ................................................... ................................................... . 165 6.7.10 service access point identifier (sapi) ...... ................................................... ............................................. 165 6.7.11 terminal endpoint identifier (tei) ........... ................................................... ................................................. 16 5 6.7.12 control field ................................ ................................................... ................................................... ................ 165 6.7.13 frame check sequence (fcs) field ............. ................................................... ............................................. 165 6.7.14 transparency (zero stuffing) .................. ................................................... ................................................ 166 6.8 transmit slc?96 data link controller .......... ................................................... ............................. 167 6.9 d/e time slot transmit hdlc controller block v5 .1 or v5.2 interface ............................ 16 8 6.10 automatic performance report (apr) ........... ................................................... ............................ 168 6.10.1 bit value interpretation .................... ................................................... ................................................... ..... 168 7.0 overhead interface block ...................... ................................................... ............................. 170 7.1 ds1 transmit overhead input interface block ... ................................................... .................... 170 7.1.1 description of the ds1 transmit overhead input interface block .................................... .......... 170 7.1.2 configure the ds1 transmit overhead input inte rface module as source of the facility data link (fdl) bits in esf framing format mode ........... ................................................... ................................. 170 7.1.3 configure the ds1 transmit overhead input interf ace module as source of the signaling framing (fs) bits in n or slc?96 framing format mode .................................................. ...................... 172 7.1.4 configure the ds1 transmit overhead input interf ace module as source of the remote sig- naling (r) bits in t1dm framing format mode ........ ................................................... ................................ 173 7.2 ds1 receive overhead output interface block ... ................................................... ................... 173 7.2.1 description of the ds1 receive overhead output i nterface block ..................................... ........ 174 7.2.2 configure the ds1 receive overhead output int erface module as destination of the facility data link (fdl) bits in esf framing format mode .... ................................................... ............................. 174 7.2.3 configure the ds1 receive overhead output int erface module as destination of the signaling framing (fs) bits in n or slc?96 framing format mode .................................................. ...................... 175 7.2.4 configure the ds1 receive overhead output inte rface module as destination of the remote signaling (r) bits in t1dm framing format mode ..... ................................................... ............................. 176 7.3 e1 overhead interface block ................... ................................................... ...................................... 177 7.4 e1 transmit overhead input interface block .... ................................................... ...................... 177 7.4.1 description of the e1 transmit overhead input interface block ................................... .............. 177 7.4.2 configure the e1 transmit overhead input inter face module as source of the national bit se- quence in e1 framing format mode ................... ................................................... ........................................ 178 7.5 e1 receive overhead interface ................. ................................................... ..................................... 180 7.5.1 description of the e1 receive overhead output i nterface block ..................................... .......... 180 7.5.2 configure the e1 receive overhead output interf ace module as source of the national bit sequence in e1 framing format mode ................ ................................................... ....................................... 181 8.0 liu transmit path ............................. ................................................... ......................................... 183 8.1 transmit diagnostic features .................. ................................................... ...................................... 183 8.1.1 taos (transmit all ones) ..................... ................................................... ................................................... ....... 183 8.1.2 ataos (automatic transmit all ones) ............. ................................................... ......................................... 184 8.1.3 network loop up code ........................ ................................................... ................................................... ........ 184 8.1.4 network loop down code ...................... ................................................... ................................................... ... 184 8.1.5 qrss generation ............................. ................................................... ................................................... ............... 185 8.2 t1 long haul line build out (lbo) ............. ................................................... ...................................... 185 8.3 t1 short haul line build out (lbo) ............ ................................................... ..................................... 186 8.3.1 arbitrary pulse generator ................... ................................................... ................................................... .. 186 8.3.2 dmo (digital monitor output) .................. ................................................... ................................................... . 187 8.3.3 transmit jitter attenuator ..................... ................................................... ................................................... 187 8.4 line termination (ttip/tring) ................. ................................................... ............................................ 188 9.0 liu receive path .............................. ................................................... ........................................... 189 9.1 line termination (rtip/rring) ................. ................................................... ........................................... 189 9.1.1 case 1: internal termination .................. ................................................... ................................................... .. 189 9.1.2 case 2: internal termination with one external fi xed resistor for all modes .................... 189 9.1.3 equalizer control ............................ ................................................... ................................................... ........... 190 9.1.4 cable loss indicator ......................... ................................................... ................................................... .......... 190 9.2 receive sensitivity ........................... ................................................... ................................................... .. 191 9.2.1 ais (alarm indication signal) ................ ................................................... ................................................... .... 191 9.2.2 nlcd (network loop code detection) ........... ................................................... ........................................... 191 9.2.3 flsd (fifo limit status detection) .............. ................................................... ............................................... 192 9.2.4 receive jitter attenuator .................... ................................................... ................................................... .... 192 9.2.5 rxmute (receiver los with data muting) ......... ................................................... ....................................... 192 10.0 the e1 transmit/receive framer ............... ................................................... ........................ 194 10.1 description of the transmit/receive payload da ta input interface block ................ 194 10.1.1 brief discussion of the transmit/receive paylo ad data input interface block operating at
xrt86l30 iii single t1/e1/j1 framer/liu combo rev. 1.0.1 xrt84v24 compatible 2.048mbit/s mode ............... ................................................... ........................................ 194 10.2 transmit/receive high-speed back-plane interfa ce ................................................ ............... 197 10.2.1 non-multiplexed high-speed mode ............ ................................................... .............................................. 197 10.2.2 multiplexed high-speed mode ................. ................................................... .................................................. 2 00 10.3 brief discussion of common channel signaling i n e1 framing format .......................... 206 10.4 brief discussion of channel associated signali ng in e1 framing format ................... 206 10.5 insert/extract signaling bits from tscr regist er ................................................ ................. 206 10.6 insert/extract signaling bits from txchn[0]_n/ txsig pin ......................................... ............. 206 10.7 enable channel associated signaling and signal ing data source control ............. 207 11.0 the ds1 transmit/receive framer .............. ................................................... .......................208 11.1 description of the transmit/receive payload da ta input interface block ................ 208 11.1.1 brief discussion of the transmit/receive paylo ad data input interface block operating at 1.544mbit/s mode ................................... ................................................... ................................................... ............ 208 11.2 transmit/receive high-speed back-plane interfa ce ................................................ ............... 211 11.2.1 t1 transmit/receive interface - mvip 2.048 mhz .................................................. .................................... 211 11.2.2 non-multiplexed high-speed mode ............ ................................................... .............................................. 212 11.2.3 multiplexed high-speed mode ................. ................................................... .................................................. 2 14 11.3 brief discussion of robbed-bit signaling in ds 1 framing format .................................. .. 220 11.3.1 configure the framer to transmit robbed-bit sign aling ............................................. .................. 220 11.3.2 insert signaling bits from tscr register .... ................................................... ....................................... 221 11.3.3 insert signaling bits from txsig_n pin ...... ................................................... ............................................ 221 12.0 alarms and error conditions .................. ................................................... .........................223 12.1 ais alarm .................................... ................................................... ................................................... .......... 223 12.2 red alarm .................................... ................................................... ................................................... ........ 225 12.3 yellow alarm ................................. ................................................... ................................................... ... 226 12.4 bipolar violation ............................ ................................................... ................................................... . 228 12.5 e1 brief discussion of alarms and error condit ions .............................................. ............. 231 12.5.1 how to configure the framer to transmit ais .. ................................................... ............................... 236 12.5.2 how to configure the framer to generate red ala rm ................................................ ................... 237 12.5.3 how to configure the framer to transmit yellow alarm ............................................ ................. 237 12.5.4 transmit yellow alarm ....................... ................................................... ................................................... ..... 238 12.5.5 transmit cas multi-frame yellow alarm ........ ................................................... .................................... 238 12.6 t1 brief discussion of alarms and error condit ions .............................................. .............. 239 12.6.1 how to configure the framer to transmit ais .. ................................................... ............................... 242 12.6.2 how to configure the framer to generate red ala rm ................................................ ................... 243 12.6.3 how to configure the framer to transmit yellow alarm ............................................ ................. 243 12.6.4 transmit yellow alarm in sf mode ............. ................................................... ............................................ 244 12.6.5 transmit yellow alarm in esf mode ........... ................................................... ............................................ 244 12.6.6 transmit yellow alarm in n mode ............. ................................................... .............................................. 244 12.6.7 transmit yellow alarm in t1dm mode .......... ................................................... .......................................... 244 13.0 performance monitoring (pmon) ................ ................................................... ......................247 13.1 receive line code violation counter (16-bit) . ................................................... .......................... 247 13.2 16-bit receive frame alignment error counter ( 16-bit) ........................................... .............. 247 13.3 receive severely errored frame counter (8-bit) .................................................. .................. 247 13.4 receive crc-6/4 block error counter (16-bit) . ................................................... ........................ 247 13.5 receive far-end block error counter (16-bit) . ................................................... ...................... 247 13.6 receive slip counter (8-bit) ................. ................................................... ............................................ 247 13.7 receive loss of frame counter (8-bit) ........ ................................................... ............................... 247 13.8 receive change of frame alignment counter (8-b it) ............................................... ............... 247 13.9 frame check sequence error counters 1, 2, and 3 (8-bit each) .................................... ..... 247 13.10 prbs error counter (16-bit) ................. ................................................... ......................................... 247 13.11 transmit slip counter (8-bit) ............... ................................................... ......................................... 247 13.12 excessive zero violation counter (16-bit) ... ................................................... ........................... 248 14.0 appendix a: ds-1/e1 framing formats .......... ................................................... .....................249 14.1 the e1 framing structure ..................... ................................................... .......................................... 249 14.1.1 fas frame ................................... ................................................... ................................................... ..................... 249 14.1.2 non-fas frame ............................... ................................................... ................................................... ................ 250 14.2 the e1 multi-frame structure ................. ................................................... ...................................... 251 14.2.1 the crc multi-frame structure ................. ................................................... .............................................. 251 14.2.2 cas multi-frames and channel associated sign aling ............................................. ......................... 253 14.3 the ds1 framing structure .................... ................................................... ......................................... 255 14.4 t1 super frame format (sf) ................... ................................................... .......................................... 256
xrt86l30 iv rev. 1.0.1 single t1/e1/j1 framer/liu combo 14.5 t1 extended superframe format (esf) .......... ................................................... ............................. 258 14.6 t1 non-signaling frame format ................ ................................................... .................................... 260 14.7 t1 data multiplexed framing format (t1dm) .... ................................................... ........................ 260 14.8 slc-96 format (slc-96) ....................... ................................................... ................................................. 26 1
xrt86l30 v single t1/e1/j1 framer/liu combo rev. 1.0.1 list of figures figure 1.: xrt86l30 1-channel ds1 (t1/e1/j1) framer /liu combo ........................................ ....................................... 1 figure 2.: simplified block diagram of the micropro cessor interface block ............................ ........................................ 21 figure 3.: intel p interface signals during progra mmed i/o read and write operations ................ ............................. 25 figure 4.: motorola p interface signals during pro grammed i/o read and write operations ............. ......................... 27 figure 5.: motorola 68k p interface signals during programmed i/o read and write operations ......... ..................... 28 figure 6.: dma mode for the xrt86l30 and a micropro cessor ............................................ .......................................... 29 figure 7.: liu transmit connection diagram using in ternal termination ................................ ..................................... 144 figure 8.: liu receive connection diagram using in ternal termination ................................ ..................................... 144 figure 9.: simplified block diagram of the transmit interface for 1:1 and 1+1 redundancy ............. ........................... 145 figure 10.: simplified block diagram of the receive interface for 1:1 and 1+1 redundancy ............. .......................... 146 figure 11.: simplified block diagram of a non-intru sive monitoring application ....................... .................................... 147 figure 12.: transmit t1/e1 serial pcm interface ... ................................................... ................................................... . 148 figure 13.: receive t1/e1 serial pcm interface .... ................................................... ................................................... . 148 figure 14.: t1 fractional interface ............... ................................................... ................................................... ............ 149 figure 15.: t1/e1 time slot substitution and contro l ................................................. ................................................... 150 figure 16.: robbed bit signaling / cas signaling .. ................................................... ................................................... . 151 figure 17.: esf / cas external signaling bus ...... ................................................... ................................................... .. 151 figure 18.: sf / slc-96 or 4-code signaling in esf / cas external signaling bus ...................... ................................ 152 figure 19.: t1/e1 overhead interface .............. ................................................... ................................................... ....... 153 figure 20.: t1 external overhead datalink bus ..... ................................................... ................................................... . 153 figure 21.: e1 overhead external datalink bus ..... ................................................... ................................................... . 154 figure 22.: simplified block diagram of the framer bypass mode ....................................... ........................................ 154 figure 23.: t1 high-speed non-multiplexed interface .................................................. ................................................. 15 5 figure 24.: e1 high-speed non-multiplexed interface .................................................. ................................................ 155 figure 25.: transmit high-speed bit multiplexed blo ck diagram ........................................ .......................................... 156 figure 26.: receive high-speed bit multiplexed bloc k diagram ......................................... .......................................... 156 figure 27.: simplified block diagram of local analo g loopback ........................................ .......................................... 157 figure 28.: simplified block diagram of remote loop back .............................................. ............................................. 157 figure 29.: simplified block diagram of digital loo pback ............................................. ................................................ 158 figure 30.: simplified block diagram of dual loopba ck ................................................ ................................................ 158 figure 31.: simplified block diagram of the framer remote line loopback .............................. .................................. 158 figure 32.: simplified block diagram of the framer local loopback .................................... ........................................ 159 figure 33.: simplified block diagram of the framer local loopback .................................... ........................................ 159 figure 34.: hdlc controllers ...................... ................................................... ................................................... ............. 160 figure 35.: lapd frame structure .................. ................................................... ................................................... ........ 163 figure 36.: block diagram of the ds1 transmit overh ead input interface of the xrt86l30 ............... ........................ 170 figure 37.: ds1 transmit overhead input interface t iming in esf framing format mode .................. ........................ 172 figure 38.: ds1 transmit overhead input timing in n or slc?96 framing format mode .................... ...................... 173 figure 39.: ds1 transmit overhead input interface m odule in t1dm framing format mode ................. ..................... 173 figure 40.: block diagram of the ds1 receive overhe ad output interface of xrt86l30 ................... ......................... 174 figure 41.: ds1 receive overhead output interface m odule in esf framing format mode .................. ....................... 175 figure 42.: ds1 receive overhead output interface t iming in n or slc?96 framing format mode .......... ................ 176 figure 43.: ds1 receive overhead output interface t iming in t1dm framing format mode ................. .................... 177 figure 44.: block diagram of the e1 transmit overhe ad input interface of xrt86l30 .................... ............................ 178 figure 45.: e1 transmit overhead input interface ti ming .............................................. ............................................... 180 figure 46.: block diagram of the e1 receive overhea d output interface of xrt86l30 .................... .......................... 180 figure 47.: e1 receive overhead output interface ti ming .............................................. ............................................. 182 figure 48.: taos (transmit all ones) .............. ................................................... ................................................... ....... 183 figure 49.: simplified block diagram of the ataos f unction ........................................... ............................................ 184 figure 50.: network loop up code generation ....... ................................................... ................................................... 184 figure 51.: network loop down code generation ..... ................................................... ................................................ 184 figure 52.: long haul line build out with -7.5db at tenuation ......................................... .............................................. 185 figure 53.: long haul line build out with -15db att enuation .......................................... .............................................. 185 figure 54.: long haul line build out with -22.5db a ttenuation ........................................ ............................................. 186 figure 55.: arbitrary pulse segment assignment .... ................................................... ................................................... 187 figure 56.: typical connection diagram using intern al termination .................................... ........................................ 188 figure 57.: typical connection diagram using inter nal termination ................................... ........................................ 189 figure 58.: typical connection diagram using one ex ternal fixed resistor ............................. .................................. 190
xrt86l30 vi rev. 1.0.1 single t1/e1/j1 framer/liu combo figure 59.: simplified block diagram of the equaliz er and peak detector .............................. ...................................... 190 figure 60.: simplified block diagram of the cable l oss indicator ..................................... ............................................ 190 figure 61.: test configuration for measuring receiv e sensitivity ..................................... ............................................ 191 figure 62.: process block for automatic loop code d etection .......................................... ........................................... 192 figure 63.: simplified block diagram of the rxmute function .......................................... .......................................... 193 figure 64.: interfacing the transmit path to local terminal equipment ................................ .......................................... 194 figure 66.: waveforms for connecting the transmit p ayload data input interface block to local terminal equipment 195 figure 65.: interfacing the receive path to local t erminal equipment ................................. .......................................... 195 figure 67.: waveforms for connecting the receive pa yload data input interface block to local terminal equipment . 196 figure 68.: transmit non-multiplexed high-speed con nection to local terminal equipment using mvip 2.04 8mbit/s, 4.096mbit/s, or 8.192mbit/s ....................... ................................................... ................................................... 197 figure 70.: waveforms for connecting the transmit n on-multiplexed high-speed input interface at mvip 2 .048mbit/s, 4.096mbit/s, and 8.192mbit/s ...................... ................................................... ................................................. 19 8 figure 69.: receive non-multiplexed high-speed conn ection to local terminal equipment using mvip 2.048 mbit/s, 4.096mbit/s, or 8.192mbit/s ....................... ................................................... ................................................... 198 figure 71.: waveforms for connecting the receive no n-multiplexed high-speed input interface at mvip 2. 048mbit/s, 4.096mbit/s, and 8.192mbit/s ...................... ................................................... ................................................. 19 9 figure 72.: interfacing xrt86l30 transmit to local terminal equipment using 16.384mbit/s, hmvip 16.384 mbit/s, and h.100 16.384mbit/s ...................................... ................................................... ................................................... ........ 202 figure 73.: interfacing xrt86l30 receive to local t erminal equipment using 16.384mbit/s, hmvip 16.384m bit/s, and h.100 16.384mbit/s ...................................... ................................................... ................................................... ........ 203 figure 74.: waveforms for connecting the transmit m ultiplexed high-speed input interface at hmvip and h.100 16.384mbit/s mode ................................. ................................................... ................................................... ... 204 figure 75.: waveforms for connecting the receive mu ltiplexed high-speed input interface at hmvip 16.38 4mbit/s mode 204 figure 76.: waveforms for connecting the receive mu ltiplexed high-speed input interface at h.100 16.38 4mbit/s mode 205 figure 77.: timing diagram of the txsig input ..... ................................................... ................................................... .. 206 figure 78.: timing diagram of the rxsig output .... ................................................... ................................................... 207 figure 79.: interfacing the transmit path to local terminal equipment ................................ .......................................... 208 figure 81.: waveforms for connecting the transmit p ayload data input interface block to local terminal equipment 209 figure 80.: interfacing the receive path to local t erminal equipment ................................. .......................................... 209 figure 82.: waveforms for connecting the receive pa yload data input interface block to local terminal equipment . 210 figure 83.: transmit non-multiplexed high-speed con nection to local terminal equipment using mvip 2.04 8mbit/s, 4.096mbit/s, or 8.192mbit/s ....................... ................................................... ................................................... 212 figure 84.: receive non-multiplexed high-speed conn ection to local terminal equipment using mvip 2.048 mbit/s, 4.096mbit/s, or 8.192mbit/s ....................... ................................................... ................................................... 212 figure 85.: waveforms for connecting the transmit n on-multiplexed high-speed input interface at mvip 2 .048mbit/s, 4.096mbit/s, and 8.192mbit/s ...................... ................................................... ................................................. 21 3 figure 86.: waveforms for connecting the receive no n-multiplexed high-speed input interface at mvip 2. 048mbit/s, 4.096mbit/s, and 8.192mbit/s ...................... ................................................... ................................................. 21 3 figure 87.: interfacing xrt86l30 transmit to local terminal equipment using 16.384mbit/s, hmvip 16.384 mbit/s, and h.100 16.384mbit/s ...................................... ................................................... ................................................... ........ 216 figure 88.: interfacing xrt86l30 receive to local t erminal equipment using 16.384mbit/s, hmvip 16.384m bit/s, and h.100 16.384mbit/s ...................................... ................................................... ................................................... ........ 217 figure 89.: waveforms for connecting the transmit m ultiplexed high-speed input interface at 12.352mbit /s mode .. 217 figure 91.: waveforms for connecting the transmit m ultiplexed high-speed input interface at hmvip and h.100 16.384mbit/s mode ................................. ................................................... ................................................... ... 218 figure 92.: waveforms for connecting the receive mu ltiplexed high-speed input interface at 12.352mbit/ s mode ... 218 figure 90.: waveforms for connecting the transmit m ultiplexed high-speed input interface at 16.384mbit /s mode .. 218 figure 95.: waveforms for connecting the receive mu ltiplexed high-speed input interface at h.100 16.38 4mbit/s mode 219 figure 93.: waveforms for connecting the receive mu ltiplexed high-speed input interface at 16.384mbit/ s mode ... 219 figure 94.: waveforms for connecting the receive mu ltiplexed high-speed input interface at hmvip 16.38 4mbit/s mode 219 figure 96.: timing diagram of the txsig_n input ... ................................................... ................................................... . 222 figure 97.: simple diagram of e1 system model ..... ................................................... .................................................. 2 31 figure 98.: generation of yellow alarm by the repea ter upon detection of line failure ................ ................................ 232 figure 99.: generation of ais by the repeater upon detection of line failure ......................... ...................................... 233 figure 100.: generation of yellow alarm by the cpe upon detection of ais originated by the repeater .. ................... 234
xrt86l30 vii single t1/e1/j1 framer/liu combo rev. 1.0.1 figure 101.: generation of cas multi-frame yellow a larm and ais16 by the repeater .................... ........................... 235 figure 102.: generation of cas multi-frame yellow a larm by the cpe upon detection of ais16 pattern s ent by the repeater 236 figure 103.: simple diagram of ds1 system model ... ................................................... ............................................... 239 figure 104.: generation of yellow alarm by the cpe upon detection of line failure .................... .................................. 240 figure 105.: generation of ais by the repeater upon detection of yellow alarm originated by the cpe .. ................... 241 figure 106.: generation of yellow alarm by the cpe upon detection of ais originated by the repeater .. ................... 242 figure 107.: single e1 frame diagram .............. ................................................... ................................................... ..... 249 figure 108.: frame/byte format of the cas multi-fra me structure ...................................... ........................................ 253 figure 109.: e1 frame format ...................... ................................................... ................................................... ........... 254 figure 110.: t1 frame format ...................... ................................................... ................................................... ........... 255 figure 111.: t1 superframe pcm format ............. ................................................... ................................................... .. 256 figure 112.: t1 extended superframe format ........ ................................................... ................................................... 258 figure 113.: t1dm frame format .................... ................................................... ................................................... ....... 260 figure 114.: framer system transmit timing diagram ................................................... .............................................. 263 figure 115.: framer system receive timing diagram ( rxserclk as an output) ............................ .......................... 264 figure 116.: framer system receive timing diagram ( rxserclk as an input) ............................. ............................ 265 figure 117.: framer system transmit overhead timing diagram .......................................... ...................................... 265 figure 118.: framer system receive overhead timing diagram (rxserclk as an output) ................... .................. 266 figure 119.: framer system receive overhead timing diagram (rxserclk as an input) .................... .................... 266 figure 120.: itu g.703 pulse template ............. ................................................... ................................................... ..... 270 figure 121.: dsx-1 pulse template (normalized ampli tude) ............................................. ............................................ 271
xrt86l30 viii rev. 1.0.1 single t1/e1/j1 framer/liu combo list of tables table 1:: list by pin number ...................... ................................................... ................................................... ................. 4 table 2:: selecting the microprocessor interface mo de ................................................ .................................................. 2 1 table 3:: xrt86l30 microprocessor interface signals that exhibit constant roles in both intel and moto rola modes .... 22 table 4:: intel mode: microprocessor interface sign als ............................................... ................................................... . 22 table 5:: motorola mode: microprocessor interface s ignals ............................................ ............................................... 23 table 6:: intel microprocessor interface timing spe cifications ....................................... ................................................ 25 table 7:: intel microprocessor interface timing spe cifications ....................................... ................................................ 27 table 8:: motorola 68k microprocessor interface tim ing specifications ................................ ......................................... 28 table 9:: xrt86l30 framer/liu register map ........ ................................................... ................................................... . 30 table 10:: register summary ....................... ................................................... ................................................... ............. 31 table 11:: clock select register e1 mode .......... ................................................... ................................................... ...... 37 table 12:: line interface control register t1 mode ................................................... ................................................... .. 38 table 13:: general purpose input/output 0 control r egister ........................................... ............................................... 38 table 14:: framing select register-e1 mode ........ ................................................... ................................................... .... 39 table 15:: framing select register-t1 mode ........ ................................................... ................................................... .... 40 table 16:: alarm generation register - e1 mode .... ................................................... ................................................... .. 41 table 17:: alarm generation register -t1 mode ..... ................................................... ................................................... .. 42 table 18:: synchronization mux register - e1 mode . ................................................... ................................................. 44 table 19:: synchronization mux register - t1 mode . ................................................... ................................................. 45 table 20:: transmit signaling and data link select register - e1 mode ................................ ........................................ 46 table 21:: transmit signaling and data link select register - t1 mode ................................ ........................................ 47 table 22:: framing control register e1 mode ....... ................................................... ................................................... ... 48 table 23:: framing control register t1 mode ....... ................................................... ................................................... ... 49 table 24:: receive signaling & data link select reg ister - e1 mode ................................... ......................................... 50 table 25:: receive signaling & data link select reg ister (rs&dlsr) t1 mode ........................... ............................... 51 table 26:: signaling change register 0 - t1 mode .. ................................................... ................................................... . 52 table 27:: signaling change register 1 ............ ................................................... ................................................... ........ 52 table 28:: signaling change register 2 ............ ................................................... ................................................... ........ 53 table 29:: signaling change register 3 ............ ................................................... ................................................... ........ 53 table 30:: receive national bits register ......... ................................................... ................................................... ........ 53 table 31:: receive extra bits register ............ ................................................... ................................................... .......... 54 table 32:: data link control register ............. ................................................... ................................................... ........... 55 table 33:: transmit data link byte count register . ................................................... ................................................... . 56 table 34:: receive data link byte count register .. ................................................... ................................................... . 57 table 35:: slip buffer control register ........... ................................................... ................................................... ........... 57 table 36:: fifo latency register .................. ................................................... ................................................... ............ 58 table 37:: dma 0 (write) configuration register ... ................................................... ................................................... ... 58 table 38:: dma 1 (read) configuration register .... ................................................... ................................................... .. 59 table 39:: interrupt control register ............. ................................................... ................................................... ............ 60 table 40:: lapd select register ................... ................................................... ................................................... ............ 60 table 41:: customer installation alarm generation r egister ........................................... ............................................... 61 table 42:: performance report control register .... ................................................... ................................................... .. 61 table 43:: gapped clock control register .......... ................................................... ................................................... ...... 62 table 44:: gapped clock control register .......... ................................................... ................................................... ...... 62 table 45:: transmit interface control register - e1 mode ............................................. ................................................. 63 table 46:: transmit interface control register - t1 mode ............................................. ................................................. 64 table 47:: receive interface control register (ricr ) - e1 mode ....................................... ............................................ 66 table 48:: receive interface control register (ricr ) - t1 mode ....................................... ............................................ 67 table 49:: ds1 test register ...................... ................................................... ................................................... .............. 68 table 50:: loopback code control register ......... ................................................... ................................................... ..... 69 table 51:: transmit loopback coder register ....... ................................................... ................................................... ... 70 table 52:: receive loopback activation code registe r ................................................. ................................................. 70 table 53:: receive loopback deactivation code regis ter ............................................... .............................................. 70 table 54:: transmit sa select register ............ ................................................... ................................................... ......... 71 table 55:: transmit sa auto control register 1 .... ................................................... ................................................... .... 71 table 56:: conditions on receive side when tsacr1 b its are enabled ................................... ..................................... 72 table 57:: transmit sa auto control register 2 .... ................................................... ................................................... .... 72 table 58:: conditions on receive side when tsacr1 b its enabled ....................................... ....................................... 73
xrt86l30 ix single t1/e1/j1 framer/liu combo rev. 1.0.1 table 59:: transmit sa4 register .................. ................................................... ................................................... ............ 73 table 60:: transmit sa5 register .................. ................................................... ................................................... ............ 74 table 61:: transmit sa6 register .................. ................................................... ................................................... ............ 74 table 62:: transmit sa7 register .................. ................................................... ................................................... ............ 74 table 63:: transmit sa8 register .................. ................................................... ................................................... ............ 74 table 64:: receive sa4 register ................... ................................................... ................................................... ............ 75 table 65:: receive sa5 register ................... ................................................... ................................................... ............ 75 table 66:: receive sa6 register ................... ................................................... ................................................... ............ 75 table 67:: receive sa7 register ................... ................................................... ................................................... ............ 75 table 68:: receive sa8 register ................... ................................................... ................................................... ............ 76 table 69:: data link control register ............. ................................................... ................................................... ........... 76 table 70:: transmit data link byte count register . ................................................... ................................................... .. 77 table 71:: receive data link byte count register .. ................................................... ................................................... .. 78 table 72:: data link control register ............. ................................................... ................................................... ........... 79 table 73:: transmit data link byte count register . ................................................... ................................................... .. 80 table 74:: receive data link byte count register .. ................................................... ................................................... .. 81 table 75:: device id register ..................... ................................................... ................................................... ............... 81 table 76:: revision id register ................... ................................................... ................................................... .............. 81 table 77:: transmit channel control register 0 to 3 1 e1 mode ......................................... ............................................ 81 table 78:: transmit channel control register 0 to 3 1 t1 mode ......................................... ............................................ 82 table 79:: transmit user code register 0 to 31 .... ................................................... ................................................... ... 82 table 80:: transmit signaling control register x - e1 mode ........................................... ................................................ 82 table 81:: transmit signaling control register x - t1 mode ........................................... ................................................ 83 table 82:: receive channel control register x (rccr 0-31) - e1 mode .................................. ..................................... 83 table 83:: receive channel control register x (rccr 0-23) - t1 mode .................................. ..................................... 84 table 84:: receive user code register x (rucr 0-31) .................................................. ................................................ 85 table 85:: receive signaling control register x (rs cr) (0-31) ........................................ ............................................. 86 table 86:: receive substitution signaling register (rssr) e1 mode .................................... ........................................ 86 table 87:: receive substitution signaling register (rssr) t1 mode .................................... ........................................ 87 table 88:: receive signaling array register 0 to 31 .................................................. ................................................... .. 87 table 89:: lapd buffer 0 control register ......... ................................................... ................................................... ....... 87 table 91:: pmon t1/e1 receive line code (bipolar) v iolation counter .................................. ...................................... 88 table 92:: pmon t1/e1 receive line code (bipolar) v iolation counter .................................. ...................................... 88 table 90:: lapd buffer 1 control register ......... ................................................... ................................................... ....... 88 table 93:: pmon t1/e1 receive framing alignment bit error counter .................................... ..................................... 89 table 94:: pmon t1/e1 receive framing alignment bit error counter .................................... ..................................... 89 table 95:: pmon t1/e1 receive severely errored fram e counter ......................................... ...................................... 89 table 96:: pmon t1/e1 receive crc-4 block error cou nter - msb ........................................ ..................................... 90 table 97:: pmon t1/e1 receive crc-4 block error cou nter - lsb ........................................ ...................................... 90 table 98:: pmon t1/e1 receive far-end block error c ounter - msb ...................................... .................................... 91 table 99:: pmon t1/e1 receive far end block error c ounter ............................................ .......................................... 91 table 100:: pmon t1/e1 receive slip counter ....... ................................................... ................................................... . 91 table 101:: pmon t1/e1 receive loss of frame counte r ................................................. ............................................ 92 table 102:: pmon t1/e1 receive change of frame alig nment counter ..................................... .................................. 92 table 103:: pmon lapd t1/e1 frame check sequence er ror counter 1 ..................................... ................................ 92 table 104:: t1/e1 prbs bit error counter msb ...... ................................................... ................................................... . 93 table 105:: t1/e1 prbs bit error counter lsb ...... ................................................... ................................................... .. 93 table 106:: t1/e1 transmit slip counter ........... ................................................... ................................................... ........ 93 table 107:: t1/e1 excessive zero violation counter msb ............................................... .............................................. 94 table 108:: t1/e1 excessive zero violation counter lsb ............................................... ............................................... 94 table 109:: t1/e1 frame check sequence error counte r 2 ............................................... ............................................ 94 table 110:: t1/e1 frame check sequence error counte r 3 ............................................... ............................................ 95 table 111:: block interrupt status register ....... ................................................... ................................................... ........ 95 table 112:: block interrupt enable register ....... ................................................... ................................................... ....... 96 table 113:: alarm & error interrupt status register .................................................. ................................................... ... 97 table 114:: alarm & error interrupt enable register - e1 mode ........................................ .............................................. 98 table 115:: alarm & error interrupt enable register -t1 mode ......................................... .............................................. 99 table 116:: framer interrupt status register e1 mod e ................................................. ................................................ 100 table 117:: framer interrupt status register t1 mod e ................................................. ................................................ 101 table 118:: framer interrupt enable register e1 mod e ................................................. ............................................... 102
xrt86l30 x rev. 1.0.1 single t1/e1/j1 framer/liu combo table 119:: framer interrupt enable register t1 mod e ................................................. ............................................... 103 table 120:: data link status register 1 ........... ................................................... ................................................... ....... 104 table 121:: data link interrupt enable register 1 . ................................................... ................................................... .. 105 table 122:: slip buffer interrupt status register ( sbisr) ............................................ ................................................. 10 6 table 123:: slip buffer interrupt enable register ( sbier) ............................................ ................................................ 107 table 124:: receive loopback code interrupt and sta tus register (rlcisr) ............................. ................................ 107 table 125:: receive loopback code interrupt enable register (rlcier) ................................. .................................. 108 table 126:: receive sa interrupt register (rsair) . ................................................... .................................................. 1 08 table 127:: receive sa interrupt enable register (r saier) ............................................ ........................................... 109 table 128:: excessive zero status register ........ ................................................... ................................................... .... 109 table 129:: excessive zero enable register ........ ................................................... ................................................... ... 110 table 130:: ss7 status register for lapd1 ......... ................................................... ................................................... ... 110 table 131:: ss7 enable register for lapd1 ......... ................................................... ................................................... .. 110 table 132:: data link status register 2 ........... ................................................... ................................................... ....... 110 table 133:: data link interrupt enable register 2 . ................................................... ................................................... .. 112 table 134:: ss7 status register for lapd2 ......... ................................................... ................................................... ... 113 table 135:: ss7 enable register for lapd2 ......... ................................................... ................................................... .. 113 table 136:: data link status register 3 ........... ................................................... ................................................... ....... 113 table 137:: data link interrupt enable register 3 . ................................................... ................................................... .. 115 table 138:: ss7 status register for lapd3 ......... ................................................... ................................................... ... 116 table 139:: ss7 enable register for lapd3 ......... ................................................... ................................................... .. 116 table 140:: customer installation alarm status regi ster .............................................. ................................................ 116 table 141:: customer installation alarm status regi ster .............................................. ................................................ 117 table 142:: microprocessor register #556 bit descri ption ............................................. ............................................... 118 table 143:: equalizer control and transmit line bui ld out ............................................ ............................................... 118 table 144:: microprocessor register #557 bit descri ption ............................................. ............................................... 121 table 145:: microprocessor register #558 bit descri ption ............................................. ............................................... 124 table 146:: microprocessor register #559 bit descri ption ............................................. ............................................... 126 table 147:: microprocessor register #560 bit descri ption ............................................. ............................................... 127 table 148:: microprocessor register #561 bit descri ption ............................................. ............................................... 128 table 149:: microprocessor register #562 bit descri ption ............................................. ............................................... 130 table 150:: microprocessor register #563 bit descri ption ............................................. ............................................... 130 table 151:: microprocessor register #564 bit descri ption ............................................. ............................................... 131 table 152:: microprocessor register #565 bit descri ption ............................................. ............................................... 131 table 153:: microprocessor register #566 bit descri ption ............................................. ............................................... 132 table 154:: microprocessor register #567 bit descri ption ............................................. ............................................... 132 table 155:: microprocessor register #568 bit descri ption ............................................. ............................................... 133 table 156:: microprocessor register #569 bit descri ption ............................................. ............................................... 133 table 157:: microprocessor register #570 bit descri ption ............................................. ............................................... 134 table 158:: microprocessor register #571 bit descri ption ............................................. ............................................... 134 table 159:: microprocessor register #700 bit descri ption - global register 0 ......................... .................................... 135 table 160:: microprocessor register #701, bit descr iption - global register 1 ........................ .................................... 135 table 161:: microprocessor register #702, bit descr iption - global register 2 ........................ .................................... 136 table 162:: microprocessor register #703, bit descr iption - global register 3 ........................ .................................... 136 table 163:: microprocessor register #704, bit descr iption - global register 4 ........................ .................................... 137 table 164:: list of the possible conditions that ca n generate interrupts, in each framer ............. .............................. 138 table 165:: address of the block interrupt status r egisters .......................................... ............................................... 139 table 166:: block interrupt status register ....... ................................................... ................................................... ...... 139 table 167:: block interrupt enable register ....... ................................................... ................................................... ..... 141 table 168:: interrupt control register ............ ................................................... ................................................... ......... 142 table 169:: framing format for pmon status inserted within lapd by initiating apr .................... ............................ 168 table 170:: random bit sequence polynomials ....... ................................................... ................................................. 18 5 table 171:: short haul line build out ............. ................................................... ................................................... ........ 186 table 172:: selecting the internal impedance ...... ................................................... ................................................... ... 189 table 173:: selecting the value of the external fix ed resistor ....................................... .............................................. 189 table 174:: the mapping of t1 frame into e1 framing format ........................................... ............................................ 211 table 175:: bit format of timeslot 0 octet within a fas e1 frame ..................................... .......................................... 249 table 176:: bit format of timeslot 0 octet within a non-fas e1 frame ................................. ...................................... 250 table 177:: bit format of all timeslot 0 octets wit hin a crc multi-frame ............................. ........................................ 251 table 178:: superframe format ..................... ................................................... ................................................... .......... 257
xrt86l30 xi single t1/e1/j1 framer/liu combo rev. 1.0.1 table 179:: extended superframe format ............ ................................................... ................................................... ... 259 table 180:: non-signaling framing format .......... ................................................... ................................................... ... 260 table 181:: slc?96 fs bit contents ................ ................................................... ................................................... ....... 261 table 182:: xrt86l30 power consumption ............ ................................................... .................................................. 2 62 table 183:: e1 receiver electrical characteristics ................................................... ................................................... .. 267 table 184:: t1 receiver electrical characteristics ................................................... ................................................... .. 268 table 185:: e1 transmit return loss requirement ... ................................................... ................................................. 26 8 table 186:: e1 transmitter electrical characteristi cs ................................................ ................................................... . 269 table 187:: t1 transmitter electrical characteristi cs ................................................ ................................................... . 269 table 188:: transmit pulse mask specification ..... ................................................... ................................................... .. 270 table 189:: dsx1 interface isolated pulse mask and corner points ..................................... ......................................... 271 table 190:: ac electrical characteristics ......... ................................................... ................................................... ........ 271
xrt86l30 4 rev. 1.0.1 single t1/e1/j1 framer/liu combo 1.0 pin list t able 1: l ist by p in n umber p in p in n ame 1 lop 2 nc 3 nc 4 dvdd 5 dgnd 6 tring 7 tvdd 8 ttip 9 tgnd 10 jtag_ring 11 jtag_tip 12 rgnd 13 rring 14 rtip 15 rvdd 16 avdd 17 agnd 18 sense 19 analog 20 vddpll 21 vddpll 22 pllgnd 23 pllgnd 24 mclkin 25 mclknout 26 rxoh 27 rxchn_4 28 rxchn_3 29 dgnd 30 rxcasync 31 rxohclk 32 rxchn_2
xrt86l30 5 single t1/e1/j1 framer/liu combo rev. 1.0.1 33 rxsync 34 nc 35 nc 36 rxchn_1 37 dvdd 38 rxchclk 39 rxcrcsync 40 rxchn_0 41 dvdd 42 rxserclk 43 rxlos 44 rxser 45 txchn_4 46 txchn_3 47 txchn_2 48 dgnd 49 txchclk 50 txchn_1 51 txoh 52 dvdd 53 txchn_0 54 txserclk 55 txser 56 dvdd 57 txohclk 58 txmsync 59 txsync 60 dgnd 61 req1 62 ack0 63 dvdd 64 req0 65 ack1 66 nc p in p in n ame
xrt86l30 6 rev. 1.0.1 single t1/e1/j1 framer/liu combo 67 nc 68 pclk 69 data0 70 data1 71 rd 72 dgnd 73 dben 74 rdy 75 addr0 76 addr1 77 addr2 78 dvdd 79 addr3 80 addr4 81 addr5 82 addr6 83 dgnd 84 addr7 85 reset 86 oscclk 87 dgnd 88 8ksync 89 addr8 90 data2 91 data3 92 dvdd 93 ale 94 addr9 95 addr10 96 int 97 addr11 98 nc 99 nc 100 blast p in p in n ame
xrt86l30 7 single t1/e1/j1 framer/liu combo rev. 1.0.1 101 data4 102 dgnd 103 data5 104 data6 105 dvdd 106 data7 107 wr 108 cs 109 dgnd 110 dgnd 111 tck 112 trst 113 tdi 114 tms 115 tdo 116 gpio1 117 gpio0 118 gpio2 119 gpio3 120 atest 121 test 122 8kextosc 123 faddr 124 iaddr 125 ptype2 126 ptype1 127 ptype0 128 txon p in p in n ame
xrt86l30 8 rev. 1.0.1 single t1/e1/j1 framer/liu combo 2.0 pin descriptions transmit serial data input s ignal n ame p in # t ype d escription txser 55 i transmit serial data input this input pin along with txserclk functions as the transmit serial input port to the framer block. ds1 mode any payload data applied to this pin will be insert ed into a ds1 frame and output onto the t1 line. if the framer is configured acco rdingly, the framing alignment bits, facility data link bits, and the crc-6 bits can be inserted to this input pin. the sig- nal applied to this input pin can be latched to the transmit payload data input inter- face on either the rising edge or the falling edge of txserclk. e1 mode any payload data applied to this pin will be insert ed into an e1 frame and output onto the e1 line. all data intended to be transpor ted via time slots 1 through 15 and time slots 17 through 31 must be applied to thi s input pin. if the framer is con- figured accordingly, data intended for time slots 0 and 16 can also be applied to this input pin. framer bypass mode in framer bypass mode, txser is used for the positi ve digital input pin to the liu. txserclk 54 i/o transmit serial clock input/output this clock signal is used by the transmit payload d ata input interface to latch the contents of the txser signal into the framer. data that is applied at the txser input can be latched on either the rising edge or t he falling edge of txserclk. ds1/e1 standard rate mode (1.544mhz/2.048mhz) if the transmit section of the framer has been conf igured to use txserclk as the timing source, then this signal will be an input. if the recovered line clock or the mclkin input pin is used as the timing source for t he transmitter, then txserclk will be an output. ds1/e1 high-speed backplane interface in high-speed backplane applications, txserclk is u sed as the timing source for the transmit line rate. framer bypass mode in framer bypass mode, txserclk is used for the tra nsmit clock to the liu. txsync 59 i/o transmit single frame sync pulse input/o utput this pin is configured to be an input if txserclk i s used as the timing reference for the transmitter. this pin is configured as an output if the recovered line clock or the mclkin input pin is used as the timing referenc e for the transmitter. ds1/e1 (txsync as an input) txsync must pulse "high" for one period of txserclk when the transmit payload data input interface is processing the first bit of an outbound ds1/e1 frame. n ote : it is imperative that the txsync input signal be sy nchronized with the txserclk input signal. ds1/e1 (txsync as an output) txsync will pulse "high" for one period of txserclk when the transmit payload data input interface is processing the first bit of an outbound ds1/e1 frame. framer bypass mode in framer bypass mode, txsync is used for the negat ive digital input pin to the liu.
xrt86l30 9 single t1/e1/j1 framer/liu combo rev. 1.0.1 txmsync/ txinclk 58 i/o multiframe sync pulse/transmit input clock this pin is a multiplexed i/o pin. when the device is configured to be in standard rate mode, this signal indicates the boundary of an outbound multi-frame. when the device is configured to be in high-speed mode, this pin functions as an input clock signal for the high-speed transmit back-plane interface. ds1/e1 standard rate mode (txmsync as an input) this pin is configured to be an input if txserclk i s used as the timing reference for the transmitter. txmsync must pulse "high" for one period of txserclk when the transmit payload data input interface is p rocessing the first bit of an out- bound ds1/e1 multi frame. n ote : it is imperative that the txmsync input signal be s ynchronized with the txserclk input signal. ds1/e1 standard rate mode (txmsync as an output) this pin is configured as an output if the recovere d line clock or the mclkin input pin is used as the timing reference for the transmi tter. txmsync will pulse "high" for one period of txserclk when the transmit payloa d data input interface is pro- cessing the first bit of an outbound ds1/e1 frame. ds1/e1 non-multiplexed high-speed backplane interfa ce in the non-multiplexed high-speed interface mode, t his pin is used as the timing source for the high-speed data applied to txser. t he non-multiplexed modes sup- ported are mvip 2.048mhz, 4.096mhz, and 8.192mhz. n ote : for ds1 mode, the ds-0 data is mapped into an e1 fr ame by ignoring every fourth time slot (dont care). ds1/e1 multiplexed high-speed backplane interface in the multiplexed high-speed interface mode, this pin is used as the timing source for the high-speed data applied to txser. the mult iplexed modes supported are 12.352mhz (ds1 only), 16.384mhz, 16.384mhz hmvip, a nd 16.384mhz h.100. for ds1 mode in 16.384mhz rate, the ds-0 data is ma pped into an e1 frame by ignoring every fourth time slot (dont car e). txchclk 49 o transmit channel clock output signal this pin indicates the boundary of each time slot o f an outbound ds1/e1 frame. ds1/e1 mode each of these output pins is 192khz/256khz clock fo r ds1/e1 respectively which pulses "high" whenever the transmit payload data in put interface block accepts the lsb of each of the 24/32 time slots. the termi nal equipment can use this clock signal to sample the txchn0 through txchn4 time slo t identifier pins. ds1/e1 fractional interface clock in the fractional interface mode, txchclk can be co nfigured to function as one of the following: the pin will output a gapped fractio nal clock that can be used by ter- minal equipment input fractional payload data using the falling edge of the clock. otherwise the fractional payload data is clocked in to the chip using the un-gapped txserclk pin. transmit serial data input s ignal n ame p in # t ype d escription
xrt86l30 10 rev. 1.0.1 single t1/e1/j1 framer/liu combo txchn_0/ txsig 53 o i transmit time slot octet identifier output-bit 0 these output signals (txchn4_n through txchn0_n) re flect the five-bit binary value of the number of the current time slot being accepted and processed by the transmit payload data input interface block. termi nal equipment can use txchclk to sample the five output pins of each channel in o rder to identify the time slot being processed. transmit serial signaling bus input these pins can be used to input robbed-bit signalin g data within an outbound ds1 frame or to input channel associated signaling (cas ) bits within an outbound e1 frame. txchn_1/ txfrtd 50 i/o transmit time slot octet identifier output-bit 1 these output signals (txchn4_n through txchn0_n) re flect the five-bit binary value of the number of time slot being accepted and processed by the transmit payload data input interface. terminal equipment c an use txchclk to sample the five output pins of each channel in order to identi fy the time slot being processed. transmit serial fractional ds1/e1 input these pins can be used to input fractional ds1/e1 p ayload data within an outbound ds1/e1 frame. in this mode, terminal equipment wil l use either txchclk or txserclk to sample fractional ds1/e1 payload data. txchn_2/ tx12mhz 47 o transmit time slot octet identifier output-bit 2 these output signals (txchn4_n through txchn0_n) re flect the five-bit binary value of the number of time slot being accepted and processed by the transmit payload data input interface block. terminal equip ment can use txchclk to sam- ple the five output pins of each channel in order t o identify the time slot being pro- cessed. if txchn1_n is configured as txfrtd_n to i nput fractional ds1/e1 payload data, the txchn2_n pin will serially output the five-bit binary value of the number of the time slot being accepted and processe d. transmit 12.352mhz clock output these pins can be used to output 12.352mhz/16.384mh z clock derived from the mclkin input pin. txchn_3/ txohsync 46 o transmit time slot octet identifier output-bit 3 : these output signals (txchn4_n through txchn0_n) re flect the five-bit binary value of the number of time slot being accepted and processed by the transmit payload data input interface block. terminal equip ment can use txchclk to sam- ple the five output pins of each channel in order t o identify the time slot being pro- cessed. transmit overhead synchronization pulse these pins can be used to output an overhead synchr onization pulse that indi- cates the first bit of each multi-frame. txchn_4 45 o transmit time slot octet identifier outpu t-bit 4: these output signals (txchn4_n through txchn0_n) re flect the five-bit binary value of the number of time slot being accepted and processed by the transmit payload data input interface block. terminal equip ment can use txchclk to sam- ple the five output pins of each channel in order t o identify the time slot being pro- cessed. transmit serial data input s ignal n ame p in # t ype d escription
xrt86l30 11 single t1/e1/j1 framer/liu combo rev. 1.0.1 overhead interface s ignal n ame p in # t ype d escription txoh 51 i transmit overhead input this input pin, along with txohclk functions as the transmit overhead input port. ds1 mode this input pin will become active if the transmit s ection has been configured to use this input as the source for the facility data link bits in esf framing mode, fs bits in the slc96 and n framing mode, and r bit in t1dm mode. the data that is input into this pin will be inserted into t he data link bits within the out- bound ds1 frames at the falling edge of txserclk. n ote : this input pin will be disabled if the framer is us ing the transmit hdlc controller, or the txser input as the source for th e data link bits. e1 mode this input pin will become active if the transmit s ection has been configured to use this input as the source for the data link bits . the data that is input into this pin will be inserted into the sa4 through sa8 bits (the national bits) within the outbound non-fas e1 frames. n ote : this input pin will be disabled if the framer is us ing the transmit hdlc controller, or the txser input as the source for th e data link bits. txohclk 57 o transmit oh serial clock output signal this output clock signal functions as a demand cloc k signal for the transmit overhead data input interface block. ds1/e1 mode if the txoh pins have been configured to be the sou rce for the facility data link bits, then the framer will provide a clock edge for each data link bit. the data link equipment can provide data to txoh on the risi ng edge of txohclk. the framer will latch the data on the falling edge of t his clock signal. rxoh 26 o receive overhead output this pin, along with rxohclk functions as the recei ve overhead output inter- face. ds1 mode this pin unconditionally outputs the contents of th e facility data link bit in esf framing mode, fs bit in the slc96 and n framing mod e, and r bit in t1dm framing mode. n ote : this output pin is active even if the receive hdlc controller is active. e1 mode this pin unconditionally outputs the contents of th e national bits (sa4 through sa8). if the framer has been configured to interpr et the national bits of the incoming e1 frames as carrying data link informatio n, then the receive over- head output interface will provide a clock pulse on rxohclk for each sa bit carrying data link information. n ote : this output pin is active even if the receive hdlc controller is active. rxohclk 31 o receive oh serial clock output signal this pin, along with rxoh functions as the receive overhead output interface. ds1/e1 mode this pin outputs a clock edge corresponding to each facility data link bit which carries data link information. the data link equip ment can sample data from rxoh on the rising edge of rxohclk. the framer wil l update the data on the falling edge of this clock signal.
xrt86l30 12 rev. 1.0.1 single t1/e1/j1 framer/liu combo receive serial data output s ignal n ame p in # t ype d escription rxsync 33 i/o receive single frame sync pulse input/ou tput this pin is configured to be an input if the slip b uffer is enabled in the receive path. otherwise, this pin is an output signal. ds1/e1 (rxsync as an input) rxsync must pulse "high" for one period of rxserclk and repeat every 125 m s. the framer will output the first bit of an inb ound ds1/e1 frame during the provided rxsync pulse. n ote : it is imperative that the rxsync input signal be sy nchronized with rxserclk. ds1/e1 (txsync as an output) rxsync will pulse "high" for one period of rxserclk when the receive pay- load data input interface is processing the first b it of an inbound ds1/e1 frame. framer bypass mode in framer bypass mode, rxsync is used for the negat ive digital output pin to the liu. rxcrcsync 39 o multiframe sync pulse output this ds1 only signal will pulse "high" for one peri od of rxserclk the instant that the receive payload data interface is processi ng the first bit of a ds1 multi- frame. rxcasync 30 o receive cas multiframe sync output signal this e1 only signal will pulse "high" for one perio d of rxserclk the instant that the receive payload data interface is processi ng the first bit of an e1 cas multi-frame. rxserclk 42 i/o receive serial clock signal this clock signal is used by the receive payload da ta output interface to latch/ update the contents of rxser. the output data on r xser can be updated on either the rising edge or the falling edge of rxser clk. this pin is configured to be an input if the slip buffer is enabled in the re ceive path. otherwise, this pin is an output signal. ds1/e1 non-multiplexed high-speed backplane interfa ce (input only) in the non-multiplexed high-speed interface mode, t his pin is used as the timing source for the high-speed output data to rxser. th e non-multiplexed modes supported are mvip 2.048mhz, 4.096mhz, and 8.192mhz . n ote : for ds1 mode, the ds-0 data is mapped into an e1 fr ame by ignoring every fourth time slot (dont care). ds1/e1 multiplexed high-speed backplane interface ( input only) in the multiplexed high-speed interface mode, this pin is used as the timing source for the high-speed output data to rxser. th e multiplexed modes sup- ported are 12.352mhz (ds1 only), 16.384mhz, 16.384m hz hmvip, and 16.384mhz h.100. for ds1 mode in 16.384mhz rate, the ds-0 data is ma pped into an e1 frame by ignoring every fourth time slot (dont car e). framer bypass mode: in framer bypass mode, rxserclk is used for the rec eive clock to the liu.
xrt86l30 13 single t1/e1/j1 framer/liu combo rev. 1.0.1 rxser 44 o receive serial data output this output pin along with rxserclk functions as th e receive serial output. ds1/e1 mode any incoming t1/e1 line data that is received from the line will be decoded and output via this pin. the framer can use either the rising edge or the falling edge of rxserclk to update the received t1/e1 payload da ta. framer bypass mode: in framer bypass mode, rxser is used for the positi ve digital output pin to the liu. rxchn_0/ rxsig 40 o receive time slot octet identifier output-bit 0 these output signals (rxchn4_n through rxchn0_n) re flect the five-bit binary value of the number of time slot being received and output to the terminal equipment via the receive payload data output inter face. the terminal equip- ment can use rxchclk to sample these five output pi ns in order to identify the time slot being processed. receive serial signaling output these pins can be used to output robbed-bit signali ng (ds1) or cas signaling (e1) extracted from an incoming ds1/e1 frame. rxchn_1/ rxfrtd 36 o receive time slot octet identifier output-bit 1 these output signals (rxchn4_n through rxchn0_n) re flect the five-bit binary value of the number of time slot being received and output to the terminal equipment via the receive payload data output inter face. the terminal equip- ment can use rxchclk to sample these five output pi ns in order to identify the time slot being processed. receive serial fractional ds1/e1 output these pins can be used to output fractional ds1/e1 payload data within an inbound ds1/e1 frame. in this mode, terminal equip ment will use either rxch- clk or rxserclk to clock out fractional ds1/e1 payl oad data. rxchn_2/ rxchn 32 o receive time slot octet identifier output-bit 2 these output signals (rxchn4_n through rxchn0_n) re flect the five-bit binary value of the number of time slot being received and output to the terminal equipment via the receive payload data output inter face. the terminal equip- ment can use rxchclk to sample these five output pi ns in order to identify the time slot being processed. receive time slot identifier serial output if rxchn1 is configured as rxfrtd to output fractio nal ds1/e1 payload data, then these pins serially output the five-bit binary value of the number of the time slot being accepted and processed by the transmit p ayload data input inter- face. rxchn_3/ rx8khz 28 o receive time slot octet identifier output-bit 3 these output signals (rxchn4_n through rxchn0_n) re flect the five-bit binary value of the number of time slot being received and output to the terminal equipment via the receive payload data output inter face. the terminal equip- ment can use rxchclk to sample these five output pi ns in order to identify the time slot being processed. receive 8khz clock output these pins can output a reference 8khz clock signal if configured accordingly. receive serial data output s ignal n ame p in # t ype d escription
xrt86l30 14 rev. 1.0.1 single t1/e1/j1 framer/liu combo rxchn_4/ rxsclk 27 o receive time slot octet identifier output-bit 4 these output signals (rxchn4_n through rxchn0_n) re flect the five-bit binary value of the number of time slot being received and output to the terminal equipment via the receive payload data output inter face. the terminal equip- ment can use rxchclk to sample these five output pi ns in order to identify the time slot being processed. receive recovered line clock output these pins output the recovered t1/e1 line clock (1 .544mhz and 2.048mhz) for each channel in the high-speed modes of operation. rxchclk 38 o receive channel clock output this pin indicates the boundary of each time slot o f an outbound ds1/e1 frame. ds1/e1 mode each of these output pins is 192khz/256khz clock fo r ds1/e1 respectively which pulses "high" whenever the receive payload da ta input interface block outputs the lsb of each of the 24/32 time slots. t he terminal equipment can use this clock signal to sample the rxchn0 through rxchn4 time slot identifier pins. ds1/e1 fractional interface clock in the fractional interface mode, rxchclk can be co nfigured to function as one of the following: the pin will output a gapped frac tional clock that can be used by terminal equipment to output fractional payload data using the rising edge of the clock. otherwise, the fractional payload data is clocked out of the chip using the un-gapped rxserclk pin. receive line interface s ignal n ame p in # t ype d escription rtip 14 i receive positive analog input rtip is the positive differential input from the li ne interface. along with the rring signal, these pins should be coupled to a 1:1 transformer for proper operation. the center tap of the receive transform er should have a bypass capacitor of 0.1 m f to ground (chip side). rring 13 i receive negative analog input rring is the negative differential input from the l ine interface. along with the rtip signal, these pins should be coupled to a 1:1 transformer for proper opera- tion. the center tap of the receive transformer sh ould have a bypass capacitor of 0.1 m f to ground (chip side). receive serial data output s ignal n ame p in # t ype d escription
xrt86l30 15 single t1/e1/j1 framer/liu combo rev. 1.0.1 rxlos 43 o receive loss of signal output indicator this output pin will toggle high (declare los) if the receive block associated with channel n determines that an rlos condition oc curs according to g.775 conversely, the xrt86l30 will "tri-state" this pin anytime (and for the duration that) the receive ds1/e1 framer or liu block is not declaring the los defect condition. n ote : since the xrt86l30 tri-states this output pin (any time the channel is not declaring the los defect condition), the user m ust connect a "pull- down" resistor (ranging from 1k to 10k) to each rxl os output pin, to pull this output pin to the logic "low" condition, whenever the channel is not declaring the los defect condition. this pin is or-ed with the liu rlos and the framer rlos bit. if either the liu rlos or the framer rlos bit pulses high, these rlos pins will be set to high. transmit line interface s ignal n ame p in # t ype d escription ttip 8 o transmit positive analog output ttip is the positive differential output to the lin e interface. along with the tring signal, these pins should be coupled to a 1:2 step up transformer for proper operation. this pin should have a series li ne capacitor of 0.68 m f. tring 6 o transmit negative analog output tring is the negative differential output to the li ne interface. along with the ttip signal, these pins should be coupled to a 1:2 step up transformer for proper operation. txon 128 i transmitter on upon power up, the transmit output (ttip/tring) is tri-stated. turning the transmitter on or off is selected by programming th e appropriate register if this pin is pulled high. if the txon pin is pulled l ow, the transmitter is tri-stated. n ote : internally pulled low with a 50k w resistor. timing interface s ignal n ame p in # t ype d escription mclkin 24 i master clock input: this pin is used to provide the timing reference fo r the internal master clock of the device. the frequency of this clock is program mable from 8khz to 16.384mhz in register 0x0fe9. mclknout 25 o liu t1/e1 output clock reference this output clock depends on the mode of operation. in t1 mode, this output pin is defaulted to 1.544mhz, but can be programmed to output 3.088mhz, 6.176mhz, or 12.352mhz in register 0x0fe4. in e1 m ode, this output pin is defaulted to 2.048mhz, but can be programmed to 4.0 96mhz, 8.192mhz, or 16.384mhz in register 0x0fe4. receive line interface s ignal n ame p in # t ype d escription
xrt86l30 16 rev. 1.0.1 single t1/e1/j1 framer/liu combo oscclk 86 o framer t1/e1 output clock reference this output clock depends on the mode of operation. in t1 mode, this output pin is defaulted to 1.544mhz, but can be programmed to output 49.408mhz in register 0x011e. in e1 mode, this output pin is de faulted to 2.048mhz, but can be programmed to 65.536mhz in register 0x011e. 8ksync 88 o 8khz clock output reference this pin is an output reference of 8khz based on th e mclkin input. therefore, the duty cycle of this output is determined by the time period of the input clock reference. 8kextosc 122 i external oscillator select for normal operation, this pin should not be used, or pulled low. n ote : this pin is internally pulled low with a 50k w resistor. analog 19 o factory test mode pin note: for internal use only lop 1 i loss of power for e1 only / input pin for mess aging gpio control s ignal n ame p in # t ype d escription gpio_3 gpio_2 gpio_1 gpio_0 119 118 116 117 i/o general purpose input/output pins the gpio pins can be used as either inputs or outpu ts selected by register 0x0102. by default, these pins are inputs. to con figure a gpio pin to be an output, the register bit must be set to 1. jtag s ignal n ame p in # t ype d escription tck 111 i test clock: boundary scan clock input. note: this input pin should be pulled low for nor mal operation tms 114 i test mode select: boundary scan mode select input. note : this input pin should be pulled low for normal operation tdi 113 i test data in: boundary scan test data input note : this input pin should be pulled low for normal operation tdo 115 o test data out: boundary scan test data output trst 112 i jtag test reset input test 121 i factory test mode pin note: user should tie this pin to ground atest 120 i factory test mode pin note: user should tie this pin to ground sense 18 i factory test mode pin note: user should tie this pin to ground timing interface s ignal n ame p in # t ype d escription
xrt86l30 17 single t1/e1/j1 framer/liu combo rev. 1.0.1 jtag_ring 10 i jtag_ring test pin jtag_tip 11 i jtag_tip test pin microprocessor interface (framer channel number indicated by ) s ignal n ame p in # t ype d escription data0 data1 data2 data3 data4 data5 data6 data7 69 70 90 91 101 103 104 106 i/o bidirectional microprocessor data bus data[7:0] is a bi-directional data bus used for rea d and write operations. n ote : this bus is used as the bi-directional data port fo r storing and retrieving information through the dma interface if enabled. req0 req1 64 61 o dma cycle request outputdma controller 0 (write) : the framer asserts this output pin (toggles it "low ") when at least one of the transmit hdlc buffers are empty and can receive one more hdlc message. the framer negates this output pin (toggles it hig h) when the hdlc buffer can no longer receive another hdlc message. dma cycle request outputdma controller 1 (read): the framer asserts this output pin (toggles it "low ") when one of the receive hdlc buffer contains a complete hdlc message that n eeds to be read by the c/p. the framer negates this output pin (toggles it high ) when the receive hdlc buffers are depleted. int 96 o interrupt request output: the framer will assert this active "low" output (to ggles it "low"), to the local p, anytime it requires interrupt service. pclk 68 i microprocessor clock input: this clock signal is the microprocessor interface s ystem clock. this clock signal is used for synchronous/dma data transfer. the maxi mum frequency of this clock signal is 33mhz. iaddr 124 i this pin must be tied low for normal ope ration. faddr 123 i this pin must be tied high for normal op eration. jtag s ignal n ame p in # t ype d escription
xrt86l30 18 rev. 1.0.1 single t1/e1/j1 framer/liu combo ptype0 ptype1 ptype2 127 126 125 i microprocessor type input: these input pins permit the user to specify which t ype of microprocessor/micro- controller to be interfaced the framer. rdy 74 o ready/data transfer acknowledge output: the exact behavior of this pin depends upon which m icroprocessor the framer is configured to interface to: intel type microprocessors this output pin toggles "low" when the framer is re ady to respond to the cur- rent pio (programmed i/o) or burst transaction. motorola type microprocessors this output pin toggles "low" when the framer has c ompleted the current bus cycle. addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 75 76 77 79 80 81 82 84 89 94 95 97 i microprocessor interface address bus input addr[11:0] is a direct address bus for permitting a ccess to internal registers for read and write operations. dben 73 i data bus enable input pin . this active-low pin is used to enable the bi-direct ional databus. to disable the databus, this pin must be pulled high. ale 93 i address latch enable input_address strobe microprocessor interface (framer channel number indicated by ) s ignal n ame p in # t ype d escription 0 1 1 m mm m ptype0 0 0 0 0 0 1 m mm m ptype1 m mm m ptype2 68hc11, 8051, 80c188 motorola 68k ibm power pc 403 microprocessor type
xrt86l30 19 single t1/e1/j1 framer/liu combo rev. 1.0.1 cs 108 i microprocessor interfacechip select input: the microprocessor/microcontroller must assert this input pin (toggle it "low") in order to exchange data with the framer. note: for the 68k mpu, this signal is generated by addres s decode and address strobe. rd 71 i microprocessor interfaceread strobe input: the exact behavior of this pin depends upon the typ e of microprocessor/micro- controller the framer has been configured to interf ace to, as defined by the m ptype[2:0] pins. wr 107 i microprocessor interfacewrite strobe input the exact behavior of this pin depends upon the typ e of microprocessor/micro- controller the framer has been configured to interf ace to, as defined by the m ptype[2:0] pins. ack0 ack1 62 65 i dma cycle acknowledge inputdma controller 0 (writ e): the external dma controller will assert this input pin low when the following two conditions are met: a. after the dma controller, within the framer has asserted (toggled low), the req_0 output signal. b. when the external dma controller is ready to tra nsfer data from external memory to the selected transmit hdlc buffer. at this point, the dma transfer between the externa l memory and the selected transmit hdlc buffer may begin. after completion of the dma cycle, the external dma controller will negate this input pin after the dma controller within the frame r has negated the req_0 out- put pin. the external dma controller must do this i n order to acknowledge the end of the dma cycle. dma cycle acknowledge inputdma controller 1 (read) : the external dma controller asserts this input pin low when the following two conditions are met: a. after the dma controller, within the framer has asserted (toggled "low"), the req_1 output signal. b. when the external dma controller is ready to tra nsfer data from the selected receive hdlc buffer to external memory. at this point, the dma transfer between the selecte d receive hdlc buffer and the external memory may begin. after completion of the dma cycle, the external dma controller will negate this input pin after the dma controller within the frame r has negated the req_1 out- put pin. the external dma controller will do this i n order to acknowledge the end of the dma cycle. blast 100 i last cycle of burst indicator input: the microprocessor asserts this pin lowwhen it is performing its last read or write cycle, within a burst operation. reset 85 i hardware reset input reset is an active low input. if this pin is pulled lo w for more than 10 m s, the device will be reset, and the internal registers wi ll be reset to their default val- ues. microprocessor interface (framer channel number indicated by ) s ignal n ame p in # t ype d escription
xrt86l30 20 rev. 1.0.1 single t1/e1/j1 framer/liu combo power supply pins s ignal n ame t ype d escription dvdd pwr framer block power supply 4, 37, 41, 52, 56, 63, 78, 92, 105 avdd pwr analog power supply for liu section 16 rvdd pwr receiver analog power supply for liu section 15 tvdd pwr transmitter analog power supply for liu sect ion 7 vddpll pwr analog power supply for pll 20, 21 ground pins s ignal n ame t ype d escription dgnd gnd framer block ground 5, 29, 48, 60, 72, 83, 87, 102, 109, 110 agnd gnd analog ground for liu section 17 rgnd gnd receiver analog ground for liu section 12 tgnd gnd transmitter analog ground for liu section 9 pllgnd gnd analog ground for pll 22, 23 no connect pins s ignal n ame t ype d escription nc nc not connected 2, 3, 34, 35, 66, 67, 98, 99
xrt86l30 21 single t1/e1/j1 framer/liu combo rev. 1.0.1 3.0 microprocessor interface block the microprocessor interface section supports commu nication between the local microprocessor (p) and the framer/liu combo. the xrt86l30 supports an intel a synchronous interface, motorola 68k asynchronous, and a motorola power pc interface. the microproces sor interface is selected by the state of the ptype [2:0] input pins. selecting the microprocessor interface is shown in table 2 . the xrt86l30 uses multipurpose pins to configure th e device appropriately. the local p configures th e framer/liu by writing data into specific addressabl e, on-chip read/write registers. the microprocesso r interface provides the signals which are required f or a general purpose microprocessor to read or writ e data into these registers. the microprocessor interface also supports polled and interrupt driven environme nts. a simplified block diagram of the microprocessor is s hown in figure 2 . 3.0.1 the microprocessor interface block signals the xrt86l30 may be configured into different operating modes a nd have its performance monitored by software through a standard microprocessor using da ta, address and control signals. these interface s ignals are described below in table 3 , table 4 , and table 5 . the microprocessor interface can be configured to operate in intel mode or motorola mode. when the mi croprocessor interface is operating in intel mode, some of the control signals function in a manner require d by the intel 80xx family of microprocessors. like wise, when the microprocessor interface is operating in motoro la mode, then these control signals function in a m anner as required by the motorola power pc family of micropr ocessors. (for using a motorola 68k asynchronous processor, see figure 5 and table 8 ) table 3 lists and describes those microprocessor interface signals whose role is constant across the two modes. table 4 describes the role of some of these signals when t he microprocessor interface is operating in the intel mode. likewise, table 5 describes the role of these signals when the microprocessor interface is operating in t he motorola mode. t able 2: s electing the m icroprocessor i nterface m ode ptype[2:0] m icroprocessor m ode 0h (000) intel 68hc11, 8051, 80c188 (asynchronous) 1h (001) motorola 68k (asynchronous) 7h (111) motorola mpc8260, mpc860 power pc (synchronous) f igure 2. s implified b lock d iagram of the m icroprocessor i nterface b lock m processor interface wr rd ale ptype [2:0] reset pclk cs addr[11:0] data[7:0] rdy int req[1:0] dben blast ack[1:0]
xrt86l30 22 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 3: xrt86l30 m icroprocessor i nterface s ignals that exhibit constant roles in both i ntel and m otorola m odes p in n ame t ype d escription ptype[2:0] i microprocessor interface mode select inp ut pins these three pins are used to specify the microproce ssor interface mode. the relationship between the state of these three input pins, and th e corresponding microprocessor mode is presented in table 2 . data[7:0] i/o bi-directional data bus for register "r ead" or "write" operations. addr[11:0] i 15-bit address bus inputs the xrt86l30 microprocessor interface uses a direct address bus. this address bus is pro- vided to permit the user to select an on-chip regis ter for read/write access. cs i chip select input this active low signal selects the microprocessor i nterface of the xrt86l30 and enables read/write operations with the on-chip register loc ations. t able 4: i ntel mode : m icroprocessor i nterface s ignals xrt86l30 p in n ame i ntel e quivalent p in t ype d escription ale ale i address-latch enable: this active high signal is used to latch the conte nts on the address bus addr[11:0]. the contents of the add ress bus are latched into the addr[11:0] inputs on the falling edge of ale. rd rd i read signal: this active low input functions as the read signal from the local p. when this pin is pulled low (if cs is low) the xrt86l30 is informed that a read operation has been requested and begins the pr ocess of the read cycle. wr wr i write signal: this active low input functions as the write signal from the local p. when this pin is pulled low (if cs is low) the xrt86l30 is informed that a write operation has been requested and begins the p rocess of the write cycle. rdy rdy o ready output: this active low signal is provided by the xrt86l30 device. it indicates that the current read or write cycle is c omplete, and the xrt86l30 is waiting for the next command.
xrt86l30 23 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 5: m otorola m ode : m icroprocessor i nterface s ignals xrt86l30 p in n ame m otorola e quivalent p in t ype d escription ale ts i transfer start: this active high signal is used to latch the conte nts on the address bus addr[11:0]. the contents of the address bus are latched into the addr[11:0] inputs on the falling edge of ts. wr r/w i read/write: this input pin from the local p is used to inform the xrt86l30 whether a read or write operation has been requeste d. when this pin is pulled high, we will initiate a read operation. when this pin is pulled low, we will initiate a write operation. rd we i write enable: this active low input functions as the read or wri te signal from the local p dependent on the state of r/w . when we is pulled low (if cs is low) the xrt86l30 begins the read or write ope ration. no pin oe i output enable: this signal is not necessary for the xrt86l30 to i nterface to the mpc8260 or mpc860 power pcs. pclk clkout i synchronous processor clock: this signal is used as the timing reference for the power pc synchronous mode. rdy ta o transfer acknowledge: this active low signal is provided by the xrt86l30 device. it indicates that the current read or writ e cycle is complete, and the xrt86l30 is waiting for the next command.
xrt86l30 24 rev. 1.0.1 single t1/e1/j1 framer/liu combo 3.1 intel mode programmed i/o access (asynchronous) if the xrt86l30 is interfaced to an intel type p, then it should be configured to operate in the inte l mode. intel type read and write operations are described below. intel mode read cycle whenever an intel-type p wishes to read the conten ts of a register, it should do the following. 1. place the address of the target register on the add ress bus input pins addr[11:0]. 2. while the p is placing this address value on the a ddress bus, the address decoding circuitry should assert the cs pin of the xrt86l30, by toggling it "low". this ac tion enables further communication between the p and the xrt86l30 microprocessor inte rface block. 3. toggle the ale input pin "high". this step enables the address bus input drivers, within the microproc es- sor interface block of the xrt86l30. 4. the p should then toggle the ale pin "low". this s tep causes the xrt86l30 to latch the contents of th e address bus into its internal circuitry. at this po int, the address of the register has now been selec ted. 5. next, the p should indicate that this current bus cycle is a read operation by toggling the rd input pin "low". this action also enables the bi-directional data bus output drivers of the xrt86l30. 6. after the p toggles the read signal "low", the xrt 86l30 will toggle the rdy output pin "low". the xrt86l30 does this in order to inform the p that t he data is available to be read by the p, and that it is ready for the next command. 7. after the p detects the rdy signal and has read the data, it can terminate the read cycle by toggling the rd input pin "high". n ote : ale can be tied high if this signal is not availa ble. the intel mode write cycle whenever an intel type p wishes to write a byte or word of data into a register within the xrt86l30, it should do the following. 1. place the address of the target register on the add ress bus input pins addr[11:0]. 2. while the p is placing this address value on the a ddress bus, the address decoding circuitry should assert the cs pin of the xrt86l30, by toggling it "low". this ac tion enables further communication between the p and the xrt86l30 microprocessor inte rface block. 3. toggle the ale input pin "high". this step enables the address bus input drivers, within the microproc es- sor interface block of the xrt86l30. 4. the p should then toggle the ale pin "low". this s tep causes the xrt86l30 to latch the contents of th e address bus into its internal circuitry. at this po int, the address of the register has now been selec ted. 5. the p should then place the byte or word that it i ntends to write into the target register, on the bi -direc- tional data bus data[7:0]. 6. next, the p should indicate that this current bus cycle is a write operation by toggling the wr input pin "low". this action also enables the bi-directional data bus input drivers of the xrt86l30. 7. after the p toggles the write signal "low", the xr t86l30 will toggle the rdy output pin "low". the xrt86l30 does this in order to inform the p that t he data has been written into the internal register loca- tion, and that it is ready for the next command. n ote : ale can be tied high if this signal is not available . the intel read and write timing diagram is shown in figure 3 . the timing specifications are shown in table 6 .
xrt86l30 25 single t1/e1/j1 framer/liu combo rev. 1.0.1 f igure 3. i ntel p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations t able 6: i ntel m icroprocessor i nterface t iming s pecifications s ymbol p arameter m in m ax u nits t 0 valid address to cs falling edge 0 - ns t 1 cs falling edge to rd assert 65 - ns t 2 rd assert to rdy assert - 90 ns na rd pulse width (t 2 ) 90 - ns t 3 cs falling edge to wr assert 65 - ns t 4 wr assert to rdy assert - 90 ns na wr pulse width (t 4 ) 90 - ns cs addr[11:0] ale = 1 data[7:0] rd wr rdy valid data for readback data available to write into the liu read operation write operation t 0 t 0 t 1 t 4 t 2 t 3 valid address valid address
xrt86l30 26 rev. 1.0.1 single t1/e1/j1 framer/liu combo 3.2 motorola mode programmed i/o access (synchronous ) if the xrt86l30 is interfaced to a motorola type p , it should be configured to operate in the motorol a mode. motorola type programmed i/o read and write operati ons are described below. motorola mode read cycle whenever a motorola type p wishes to read the cont ents of a register, it should do the following. 1. place the address of the target register on the add ress bus input pins addr[11:0]. 2. while the p is placing this address value on the a ddress bus, the address decoding circuitry should assert the cs pin of the xrt86l30, by toggling it "low". this ac tion enables further communication between the p and the xrt86l30 microprocessor inte rface block. 3. the p should then toggle the ts pin "low". this st ep causes the xrt86l30 to latch the contents of the address bus into its internal circuitry. at this po int, the address of the register has now been selec ted. 4. next, the p should indicate that this current bus cycle is a read operation by pulling the r/w input pin "high". 5. toggle the we input pin "low". this action enables the bi-direct ional data bus output drivers of the xrt86l30. 6. after the p toggles the we signal "low", the xrt86l30 will toggle the ta output pin "low". the xrt86l30 does this in order to inform the p that t he data is available to be read by the p, and that it is ready for the next command. 7. after the p detects the ta signal and has read the data, it can terminate the read cycle by toggling the we input pin "high". motorola mode write cycle whenever a motorola type p wishes to write a byte or word of data into a register within the xrt86l30 , it should do the following. 1. place the address of the target register on the add ress bus input pins addr[11:0]. 2. while the p is placing this address value on the a ddress bus, the address decoding circuitry should assert the cs pin of the xrt86l30, by toggling it "low". this ac tion enables further communication between the p and the xrt86l30 microprocessor inte rface block. 3. the p should then toggle the ts pin "low". this st ep causes the xrt86l30 to latch the contents of the address bus into its internal circuitry. at this po int, the address of the register has now been selec ted. 4. next, the p should indicate that this current bus cycle is a write operation by pulling the r/w input pin "low". 5. toggle the we input pin "low". this action enables the bi-direct ional data bus output drivers of the xrt86l30. 6. after the p toggles the we signal "low", the xrt86l30 will toggle the ta output pin "low". the xrt86l30 does this in order to inform the p that t he data has been written into the internal register loca- tion, and that it is ready for the next command. 7. after the p detects the ta signal and has read the data, it can terminate the read cycle by toggling the we input pin "high". the motorola read and write timing diagram is shown in figure 4 . the timing specifications are shown in table 7 .
xrt86l30 27 single t1/e1/j1 framer/liu combo rev. 1.0.1 f igure 4. m otorola p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations t able 7: i ntel m icroprocessor i nterface t iming s pecifications s ymbol p arameter m in m ax u nits t 0 valid address to cs falling edge 0 - ns t 1 cs falling edge to we assert 0 - ns t 2 we assert to ta assert - 90 ns na we pulse width (t 2 ) 90 - ns t 3 cs falling edge to ts falling edge 0 - t dc m pclk duty cycle 40 60 % t cp m pclk clock period 20 - ns cs addr[11:0] data[7:0] we r/w ta valid data for readback data available to write into the liu read operation write operation t 0 t 0 t 1 t 2 valid address valid address t 3 t 3 t 1 t 2 ts upclk t cp t dc
xrt86l30 28 rev. 1.0.1 single t1/e1/j1 framer/liu combo 3.2.1 dma read/write operations the xrt86l30 framer contains two dma controller int erfaces which provide support for all four framers within the chip. the purpose of the two dma controllers is to facilitate the rapid block transfer of data bet ween an external memory location and the on-chip hdlc buffe rs via the microprocessor interface. dma-0 write dma interface dma 0 controller interface handles data transfer be tween external memory and the selected transmit hdl c buffer. the dma cycle starts when the xrt86l30 asserts the req 0 output pin. the external dma controller then responds by asserting the ack0 input pin. the contents of the microprocessor inte rface bi-directional data bus are latched into the xrt86l30 each time the wr (write strobe) input pin is strobed low. the xrt86l30 ends the dma cycle by negating the dma request input (req 0) while wr is still active. the external dma controller acknowledges the end of dma transfer by driving the ack0 input pin high. f igure 5. m otorola 68k p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations t able 8: m otorola 68k m icroprocessor i nterface t iming s pecifications s ymbol p arameter m in m ax u nits t 0 valid address to cs falling edge 0 - ns t 1 cs falling edge to ds (pin rd _we ) assert 65 - ns t 2 ds assert to dtack assert - 90 ns na ds pulse width (t 2 ) 90 - ns t 3 cs falling edge to as (pin ale_ts) falling edge 0 - ns cs addr[11:0] ale _ts data[7:0] rd _we wr _r/w rdy _dtack valid data for readback data available to write into the liu read operation write operation t 0 t 0 t 1 t 2 motorola asychronous mode valid address valid address t 3 t 3 t 1 t 2
xrt86l30 29 single t1/e1/j1 framer/liu combo rev. 1.0.1 f igure 6. dma m ode for the xrt86l30 and a m icroprocessor req[1:0] ack[1:0] wr rd m pclk data[7:0] microprocessor xrt86l30
xrt86l30 30 rev. 1.0.1 single t1/e1/j1 framer/liu combo 3.3 memory mapped i/o addressing t able 9: xrt86l30 f ramer /liu r egister m ap a ddress [11:0] c ontents 0100h - 01ffh control register (framer block) 0300h - 03ffh time slot (payload) control (framer bl ock) 0500h - 05ffh receive signaling array (framer block) 0600h - 06ffh lapdn buffer 0 (framer block) 0700h - 07ffh lapdn buffer 1 (framer block) 0900h - 09ffh performance monitor (framer block) 0b00h - 0bffh interrupt generation/enable (framer bl ock) 0c00h - 0dffh reserved 0f00h - 0fffh line interface control (liu block)
xrt86l30 31 single t1/e1/j1 framer/liu combo rev. 1.0.1 3.4 description of the control registers t able 10: r egister s ummary r eg # f unction s ymbol h ex m ode control registers (0x0100 - 0x01ff) 0 clock and select register csr 0x0100 t1/e1 1 line interface control register licr 0x0101 t1/e1 2 general purpose input/output control gpiocr 0x0102 t1 /e1 3 reserved - 0x0103 - 4 reserved - 0x0104 - 5 reserved - 0x0105 - 6 reserved - 0x0106 - 7 framing select register fsr 0x0107 e1 framing select register 0x0107 t1 8 alarm generation register agr 0x0108 e1 alarm generation register 0x0108 t1 9 synchronization mux register smr 0x0109 e1 synchronization mux register 0x0109 t1 10 transmit signaling and data link select register t sdlsr 0x010a e1 transmit signaling and data link select register 0x010a t1 11 framing control register fcr 0x010b e1 framing control register 0x010b t1 12 receive signaling & data link select register rs&d lsr 0x010c e1 receive signaling & data link select register 0x010c t1 13 signaling change register 0 scr0 0x010d t1/e1 14 signaling change register 1 scr1 0x010e t1/e1 15 signaling change register 2 scr2 0x010f t1/e1 16 signaling change register 3 scr3 0x0110 e1 17 receive national bits register rnbr 0x0111 e1 18 receive extra bits register rebr 0x0112 e1 receive interface control ricr 0x0112 t1 19 data link control register 1 dlcr1 0x0113 t1/e1 20 transmit data link byte count register 1 tdlbcr1 0x 0114 t1/e1 21 receive data link byte count register 1 rdlbcr1 0x0 115 t1/e1 22 slip buffer control register sbcr 0x0116 t1/e1
xrt86l30 32 rev. 1.0.1 single t1/e1/j1 framer/liu combo 23 fifo latency register fifolr 0x0117 t1/e1 24 dma 0 (write) configuration register d0wcr 0x0118 t1 /e1 25 dma 1 (read) configuration register d1cr 0x0119 t1/e 1 26 interrupt control register icr 0x011a t1/e1 27 lapd select register lapdsr 0x011b t1/e1 28 customer installation alarm generation register ci agr 0x011c t1 29 performance report control register prcr 0x011d t1 30 gapped clock control register gccr 0x011e t1/e1 31 multiplexed high-speed channel control register mh sccr 0x011f t1/e1 32 transmit interface control register ticr 0x0120 e1 transmit interface control register 0x0120 t1 33 receive interface control register ricr 0x0122 e1 receive interface control register 0x0122 t1 34 ds1 test register: prbs control & status ds1tr 0x01 23 t1 35 loopback code control register lccr 0x0124 t1/e1 36 transmit loopback code register tlcr 0x0125 t1/e1 37 receive loopback activation code register rlacr 0x0 126 t1/e1 38 receive loopback deactivation code register rldcr 0 x0127 t1/e1 39 transmit sa select register tsasr 0x0130 t1/e1 40 transmit sa auto control register 1 tsacr1 0x0131 t1 /e1 41 transmit sa auto control register 2 tsacr2 0x0132 t1 /e1 42 transmit sa4 register tsa4r 0x0133 t1/e1 43 transmit sa5 register tsa5r 0x0134 t1/e1 44 transmit sa6 register tsa6r 0x0135 t1/e1 45 transmit sa7 register tsa7r 0x0136 t1/e1 46 transmit sa8 register tsa8r 0x0137 t1/e1 47 receive sa4 register rsa4r 0x013b t1/e1 48 receive sa5 register rsa5r 0x013c t1/e1 49 receive sa6 register rsa6r 0x013d t1/e1 50 receive sa7 register rsa7r 0x013e t1/e1 51 receive sa8 register rsa8r 0x013f t1/e1 52 data link control register 2 dlcr2 0x0143 t1/e1 53 transmit data link byte count register 2 tdlbcr2 0x 0144 t1/e1 t able 10: r egister s ummary r eg # f unction s ymbol h ex m ode
xrt86l30 33 single t1/e1/j1 framer/liu combo rev. 1.0.1 54 receive data link byte count register 2 rdlbcr2 0x0 145 t1/e1 55 data link control register 3 dlcr3 0x0153 t1/e1 56 transmit data link byte count register 3 tdlbcr3 0x 0154 t1/e1 57 receive data link byte count register 3 rdlbcr3 0x0 155 t1/e1 58 device id register devid 0x01fe t1/e1 59 version number register revid 0x01ff t1/e1 time slot (payload) control (0x0300 - 0x03ff) 60-91 transmit channel control register 0-31 tccr 0-3 1 0x0300 to 0x031f e1 transmit channel control register 0-23 tccr 0-23 t1 92-123 user code register 0-31 tucr 0-31 0x0320 to 0x033f e1 user code register 0-23 tucr 0-23 t1 124- 155 transmit signaling control register 0 -31 tscr 0-31 0 x0340 to 0x035f e1 transmit signaling control register 0-23 tscr 0-23 t1 156- 187 receive channel control register 0-31 rccr 0-31 0x036 0 to 0x037f e1 receive channel control register 0-31 rccr 0-23 t1 188- 219 receive user code register 0-31 rucr 0-31 0x0380 to 0x039f e1 receive user code register 0-31 rucr 0-23 t1 220- 251 receive signaling control register 0-31 rscr 0-31 0x0 3a0 to 0x03bf e1 receive signaling control register 0-23 rscr 0-23 t1 252- 283 receive substitution signaling register 0-31 rssr 0- 31 0x03c0 to 0x03df e1 receive substitution signaling register 0-23 rssr 0- 23 t1 receive signaling array (0x0500 - 0x051f) 284- 315 receive signaling array register 0 rsar0-31 0x0500 to 0x051f t1/e1 lapdn buffer 0 (0x0600 - 0x0660) t able 10: r egister s ummary r eg # f unction s ymbol h ex m ode
xrt86l30 34 rev. 1.0.1 single t1/e1/j1 framer/liu combo 316- 411 lapd buffer 0 control register lapdbcr0 0x0600 to 0x0660 t1/e1 lapdn buffer 1 (0x0700 - 0x0760) 412- 507 lapd buffer 1 control register lapdbcr1 0x0700 to 0x0760 t1/e1 performance monitor 508 t1/e1 receive line code violation counter: msb t1 /e1 rlcvcu 0x0900 t1/e1 509 t1/e1 receive line code violation counter: lsb t1 /e1 rlcvcl 0x0901 t1/e1 510 t1/e1 receive frame alignment error counter: msb t1/e1 rfbecu 0x0902 t1/e1 511 t1/e1 receive frame alignment error counter: lsb t1/e1 rfaecl 0x0903 t1/e1 512 t1/e1 receive severely errored frame counter t1/e 1rsefc 0x0904 t1/e1 513 t1/e1 receive synchronization bit (crc-6 (t1) cr c-4 (e1) block) error counter: msb t1/e1 rsbbecu 0x0905 t1/e1 514 t1/e1 receive synchronization bit (crc-6 (t1) cr c-4 (e1) block) error counter: lsb t1/e1 rsbbecl 0x0906 t1/e1 515 t1/e1 receive far-end block error counter: msb t1 /e1 rfebecu 0x0907 t1/e1 516 t1/e1 receive far-end block error counter: lsb t1 /e1 rfebecl 0x0908 e1 517 t1/e1 receive slip counter t1/e1rsc 0x0909 t1/e1 518 t1/e1 receive loss of frame counter t1/e1 rlfc 0x0 90a t1/e1 519 t1/e1 receive change of frame alignment counter t1/e1 rcoac 0x090b t1/e1 520 lapd frame check sequence error counter 1 lfcsec1 0x090c t1/e1 521 t1/e1 prbs bit error counter: msb t1/e1 pbecu 0x09 0d t1/e1 522 t1/e1 prbs bit error counter: lsb t1/e1 pbecl 0x09 0e t1/e1 523 t1/e1 transmit slip counter t1/e1tsc 0x090f t1/e1 524 t1/e1 excessive zero violation counter: msb t1/e1 ezvcu 0x910 t1/e1 525 t1/e1 excessive zero violation counter: lsb t1/e1 ezvcl 0x911 t1/e1 526 lapd frame check sequence error counter 2 lfcsec2 0x91c t1/e1 527 lapd frame check sequence error counter 3 lfcsec3 0x92c t1/e1 interrupt generation/enable register address map (0 x0b00 - 0x0b41) 528 block interrupt status register bisr 0x0b00 t1/e1 529 block interrupt enable register bier 0x0b01 t1/e1 530 alarm & error interrupt status register aeisr 0x0b 02 t1/e1 t able 10: r egister s ummary r eg # f unction s ymbol h ex m ode
xrt86l30 35 single t1/e1/j1 framer/liu combo rev. 1.0.1 531 alarm & error interrupt enable register aeier 0x0b 03 e1 alarm & error interrupt enable register 0x0b03 t1 532 framer interrupt status register fisr 0x0b04 e1 framer interrupt status register 0x0b04 t1 533 framer interrupt enable register fier 0x0b05 e1 framer interrupt enable register 0x0b05 t1 534 data link status register 1 dlsr1 0x0b06 t1/e1 535 data link interrupt enable register 1 dlier1 0x0b0 7 t1/e1 536 slip buffer interrupt status register sbisr 0x0b08 t1/e1 537 slip buffer interrupt enable register sbier 0x0b09 t1/e1 538 receive loopback code interrupt and status regis ter rlcisr 0x0b0a t1/e1 539 receive loopback code interrupt enable register r lcier 0x0b0b t1/e1 540 receive sa (sa6) interrupt status register rsaisr 0x0b0c t1/e1 541 receive sa (sa6) interrupt enable register rsaier 0x0b0d t1/e1 542 excessive zero status register exzsr 0x0b0e t1/e1 543 excessive zero enable register exzer 0x0b0f t1/e1 544 ss7 status register for lapd 1 ss7sr1 0x0b10 t1 545 ss7 enable register for lapd 1 ss7er1 0x0b11 t1 546 data link status register 2 dlsr2 0x0b16 t1/e1 547 data link interrupt enable register 2 dlier2 0x0b1 7 t1/e1 548 ss7 status register for lapd 2 ss7sr2 0x0b18 t1 549 ss7 enable register for lapd 2 ss7er2 0x0b19 t1 550 data link status register 3 dlsr3 0x0b26 t1/e1 551 data link interrupt enable register 3 dlier3 0x0b2 7 t1/e1 552 ss7 status register for lapd 3 ss7sr3 0x0b28 t1 553 ss7 enable register for lapd 3 ss7er3 0x0b29 t1 554 customer installation alarm status register ciasr 0x0b40 t1 555 customer installation alarm interrupt enable reg ister ciaier 0x0b41 t1 t able 10: r egister s ummary r eg # f unction s ymbol h ex m ode
xrt86l30 36 rev. 1.0.1 single t1/e1/j1 framer/liu combo liu register summary - channel control registers 556 to 571 channel 0 liu control register c0liucr 0x0f00 to 0x0f0f t1/e1 572 to 699 reserved - 0x0f10 to 0x0fdf liu register summary - global control registers 700 liu global control register 0 liugcr0 0x0fe0 t1/e1 701 liu global control register 1 liugcr1 0x0fe1 t1/e1 702 liu global control register 2 liugcr2 0x0fe2 t1/e1 703 liu global control register 3 liugcr3 0x0fe4 t1/e1 704 liu global control register 4 liugcr4 0x0fe9 t1/e1 705 to 731 reserved - 0x0fea to 0x0fff - t able 10: r egister s ummary r eg # f unction s ymbol h ex m ode
xrt86l30 37 single t1/e1/j1 framer/liu combo rev. 1.0.1 3.4.1 register descriptions t able 11: c lock s elect r egister e1 m ode r egister 0 - t1/e1 m ode c lock s elect r egister (csr) h ex a ddress : 0 x 0100 b it f unction t ype d efault d escription -o peration 7 bpvi r/w 0 bipolar violation insertion this bit is used to force a single bpv on the trans mit output of ttip/ tring upon the transition from 0 to 1. 0 = disabled 1 = insert bpv 6 ist1 r/w 1 t1/e1 mode select this bit is used to program the chip to either t1 o r e1 mode. 1 = t1 mode 0 = e1 mode. 5 8khz r/w 0 8khz sync enable this bit allows the user to configure the transmit sectionof the framer block to synchronize their frame alignment with the 8khz signal derived from the mclkin input pin. n ote : this bit-field is ignored if txserclk or the recove red line clock is used as the timing reference for the transmit se ction. 4 cldet r/w 0 clock loss detect enable/disable select this bit enables a protection feature for the frame r whenever the recovered line clock is used as the timing source f or the transmit sec- tion. if the liu loses clock recovery, the clock d istribution block will detect this occurrence and automatically begin to u se the liuclk derived from mclkin as the transmit source, until t he liu is able to regain clock recovery. 0 = disabled 1 = enabled 3:2 reserved r/w 0 reserved 1:0 css[1:0] r/w 00 clock source select these bits specify the timing source for the transm it framer block. 00 = rxlineclk - the recovered line clock is chosen as the timing refer- ence for the transmit section of the framer (loop t iming). 01 = txserclk - the transmit serial input clock is chosen as the tim- ing reference for the timing source for the transmi t section of the framer. 10 = liuclk - (derived from mclkin) is chosen as th e timing refer- ence for the transmit section of the framer. 11 = rxlineclk - the recovered line clock is chosen as the timing refer- ence for the transmit section of the framer (loop t iming).
xrt86l30 38 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 12: l ine i nterface c ontrol r egister t1 m ode r egister 1 - t1/e1 m ode l ine i nterface c ontrol r egister (licr) h ex a ddress : 0 x 0101 b it f unction t ype d efault d escription -o peration 7 force_los r/w 0 force transmit los this bit is used to force los to the transmit outpu t. 0 = disabled 1 = los enabled 6 reserved r/w 0 reserved 5:4 lb[1:0] r/w 0 framer loopback selection (for liu lo opback modes, see the liu configuration registers) these two bits are used to select any of the follow ing loop-back modes. 00 = no loopback 01 = local loopback 10 = remote line loopback 11 = payload loopback 3:2 reserved r/w 0 reserved 1 encode ami/b8zs r/w 0 encode ami or b8zs/hdb3 line co de select configures the transmit liu interface block to tran smit data via the ami or b8zs/hdb3 line codes. 0 = b8zs for ds1/hdb3 for e1 1 = ami line code. 0 decode ami/b8zs r/w 0 decode ami or b8zs/hdb3 line co de select enables or disables the hdb3 decoder with in the re ceive liu inter- face block. 0 = enables the b8zs/hdb3 decoder 1 = disables the b8zs/hdb3 decoder t able 13: g eneral p urpose i nput /o utput 0 c ontrol r egister r egister 2 g eneral p urpose i nput /o utput 0 c ontrol r egister (gpiocr) h ex a ddress : 0 x 0102 b it f unction t ype d efault d escription -o peration 7 gpio0_3dir r/w 0 gpio0_3 direction this bit is used to select pin gpio0_3 as an input or output. 0 = input 1 = output 6 gpio0_2dir r/w 0 gpio0_2 direction this bit is used to select pin gpio0_2 as an input or output. 0 = input 1 = output 5 gpio0_1dir r/w 0 gpio0_1 direction this bit is used to select pin gpio0_1 as an input or output. 0 = input 1 = output
xrt86l30 39 single t1/e1/j1 framer/liu combo rev. 1.0.1 4 gpio0_0dir r/w 0 gpio0_0 direction this bit is used to select pin gpio0_0 as an input or output. 0 = input 1 = output 3 gpio0_3 r/w 0 gpio0_3 control if gpio0_3dir is set to 0, this bit is a read onl y register which is used to report the state of the gpio0_3 input pin. if g pio0_3dir is set to 1, this bit is a write only register which is use d to determine the output voltage of the gpio0_3 pin. 2 gpio0_2 r/w 0 gpio0_2 control if gpio0_2dir is set to 0, this bit is a read onl y register which is used to report the state of the gpio0_2 input pin. if g pio0_2dir is set to 1, this bit is a write only register which is use d to determine the output voltage of the gpio0_2 pin. 1 gpio0_1 r/w 0 gpio0_1 control if gpio0_1dir is set to 0, this bit is a read onl y register which is used to report the state of the gpio0_1 input pin. if g pio0_1dir is set to 1, this bit is a write only register which is use d to determine the output voltage of the gpio0_1 pin. 0 gpio0_0 r/w 0 gpio0_0 control if gpio0_0dir is set to 0, this bit is a read onl y register which is used to report the state of the gpio0_0 input pin. if g pio0_0dir is set to 1, this bit is a write only register which is use d to determine the output voltage of the gpio0_0 pin. t able 14: f raming s elect r egister -e1 m ode r egister 7- e1 m ode f raming s elect r egister (fsr) h ex a ddress : 0 x 0107 b it f unction t ype d efault d escription -o peration 7 e1 modenb r/w 0 annex b enable this bit forces the framing synchronizer to be comp liant with itu-t g.706 annex b for crc-to-non-crc interworking detec tion. 0 = normal operation. 1 = annex b is enabled. 6 e1 crcdiag r/w 0 crc diagnostics select enable/disable this read/write bit-field is used to force an error ed crc pattern in the outbound crc multiframe to be sent on the trans mission line. the transmit section will implement this error by i nverting the value of crc bit (c1) 0 = transmit e1 framer functions normally (no error s) 1 = transmits errored crc bit n ote : this bit-field is ignored if crc multi-framing is d isabled. t able 13: g eneral p urpose i nput /o utput 0 c ontrol r egister r egister 2 g eneral p urpose i nput /o utput 0 c ontrol r egister (gpiocr) h ex a ddress : 0 x 0102 b it f unction t ype d efault d escription -o peration
xrt86l30 40 rev. 1.0.1 single t1/e1/j1 framer/liu combo 5 e1 cassel(1) r/w 0 cas multiframe alignment algorithm select allows the user to select which cas multiframe alig nment algorithm to employ. 00 = cas multiframe alignment disabled 01 = cas multiframe alignment algorithm 1 enabled 10 = cas multiframe alignment algorithm 2 (g.732) e nabled 11 = cas multiframe alignment disabled 4 e1 cassel(0) r/w 0 3 e1 crcsel(1) r/w 0 crc multiframe alignment criteria s elect allows the user to select which crc-multiframe alig nment to employ. 00 = crc multiframe alignment disabled 01 = crc multiframe alignment enabled. alignment is declared if at least one valid crc multiframe alignment signal (0, 0,1,0,1,1,e1,e2) is observed within 8ms. 10 = crc multiframe alignment enabled. alignment is declared if at least two valid crc multiframe alignment signals (0 ,0,1,0,1,1,e1,e2) are observed within 8ms with the time separating th e two alignment signals being multiples of 2ms. 11:crc multiframe alignment enabled. alignment is d eclared if at least 3 valid crc multiframe alignment signals (0,0 ,1,0,1,1,e1,e2) are observed within 8ms with the time separating th e two alignment signals being multiples of 2ms. 2 e1 crcsel(0) r/w 0 1 e1 ckseq_enb r/w 0 check sequence enable-fas alignment enable/disable frame check sequence in fas alignmen t process. 0 = disables frame check sequence 1 = enables frame check sequence 0 e1 fassel r/w 0 fas alignment algorithm select specifies which algorithm the receive e1 framer blo ck uses in its search for fas alignment. 0 = algorithm 1 1 = algorithm 2 t able 15: f raming s elect r egister -t1 m ode r egister 7- t1 m ode f raming s elect r egister (fsr) h ex a ddress : 0 x 0107 b it f unction t ype d efault d escription -o peration 7 sigframe r/w 0 enable signaling update setting this bit to 1 will enable signaling update (transmit and receive) on the superframe boundary. otherwise, si gnaling data will be updated once it is received. 6 crcdiag r/w 0 force crc errors setting this bit to 1 will force crc error on trans mit stream. t able 14: f raming s elect r egister -e1 m ode r egister 7- e1 m ode f raming s elect r egister (fsr) h ex a ddress : 0 x 0107 b it f unction t ype d efault d escription -o peration
xrt86l30 41 single t1/e1/j1 framer/liu combo rev. 1.0.1 5 j1_crc r/w 0 crc calculation in j1 mode setting this bit to 1 will force crc calculation fo r j1 format. the j1 crc6 calculation is based on the actual values of a ll 4632 bits in a ds1 multiframe including fe bits instead of assumin g all fe bits to be a one in t1 format. 4 oneonly r/w 0 allow only one sync candidate setting this bit to 1 will enable framing search en gine to declare sync while there is one and only one candidate left. 3 fastsync r/w 1 faster sync algorithm setting this bit to 1 will enable framing search en gine to declare sync condition earlier. 21 0 fs[2] fs[1] fs[0] r/w r/w r/w 00 0 framing select bit 2 framing select bit 1 framing select bit 0 these three bits select the ds1 framing mode. bit 2 is msb and bit 0 is lsb. n ote : changing framing format will cause a resync to be generated automatically. t able 16: a larm g eneration r egister - e1 m ode r egister 8 -e1 m ode a larm g eneration r egister (agr) h ex a ddress : 0 x 0108 b it f unction t ype d efault d escription -o peration 7 auxpg ro 0 auxp generation enables the generation of auxp pattern which is an unframed 1010. pattern. 0 = auxp is disabled. 1 = auxp is enabled. 6 lof r/w 0 loss of frame declaration criteria this read/write bit-field is used to select the lof or red alarm gener- ation criteria the receive e1 framer block will emp loy. 0 = receive e1 framer declares red alarm unless bot h fas and multi- frame alignment are achieved. 1 = prevents receive e1 framer from declaring red a larm condition; fas alignment is maintained. t able 15: f raming s elect r egister -t1 m ode r egister 7- t1 m ode f raming s elect r egister (fsr) h ex a ddress : 0 x 0107 b it f unction t ype d efault d escription -o peration framing fs[2] fs[1] fs[0] esf 0 x x sf 1 0 1 n 1 1 0 t1dm 1 1 1 slc ? ?? ? 96 1 0 0
xrt86l30 42 rev. 1.0.1 single t1/e1/j1 framer/liu combo 5 yel(1) r/w 0 yellow alarm and multiframe yellow alarm generation these bits activate and deactivate the transmission of a yellow alarm. the yellow alarm and multiframe yellow alarm data p attern can be injected either automatically upon detection of the loss of alignment or controlled by yel bits. setting these bits to b01 will enable automatic yellow alarm transmission in response to a loss of frame alignment (fas red alarm) and multiframe yellow alarm is tran smitted in response to a loss of multiframe alignment (cas red alarm). the decoding of these bits are explained as follows: 00 = disable the transmission of yellow alarm. 01 = enable automatic yellow alarm generation. 1. the yellow alarm bits (bit 3 of non-fas frames i n ts0) is transmitted by echoing the receive fas alignment status. logic one is transmitted if loss of fas alignment occurred. 2. the multiframe yellow alarm bits (bit 6 of frame 0 in ts16) is trans- mitted by echoing the receive cas multiframe alignm ent status. logic one is transmitted if loss of cas multiframe alignm ent occurred. 10 = yellow and multiframe yellow alarms are trans mitted as 0. 11 = yellow and multiframe yellow alarms are trans mitted as 1. 4 yel(0) r/w 0 3 aisg(1) r/w 0 ais generation select these read/write bit-fields are used to configure t he channel to gener- ate and transmit an ais pattern, as described below . 00 = no ais alarm generated 01 = enable unframed ais alarm generation 10 = enable ais16 generation 11 = enable framed ais alarm generation 2 aisg(0) r/w 0 1 aisd(1) r/w 0 ais pattern detection select these read/write bit-fields are used to specify the type of ais pattern that the receive e1 framer block will detect as des cribed below. 00 = ais alarm detection is disabled. 01 = enable unframed ais alarm detection. 10 = enable ais 16 detection. 11 = enable framed ais alarm detection. 0 aisd(0) r/w 0 t able 17: a larm g eneration r egister -t1 m ode r egister 8 - t1 m ode a larm g eneration r egister (agr) h ex a ddress : 0 x 0108 b it f unction t ype d efault d escription -o peration 7 reserved - - reserved 6 lof r/w 0 loss of frame declaration criteria a red alarm is generated by the receiver to indicat e the loss of frame (lof) alignment. a yellow alarm is then returned t o the remote trans- mitter to report that the receiver detects lof. se tting this bit will set the criteria for preventing red alarm from generation a s long as the frame is aligned. otherwise, the frame and multiframe must be both aligned in order to keep red alarm from happening. t able 16: a larm g eneration r egister - e1 m ode r egister 8 -e1 m ode a larm g eneration r egister (agr) h ex a ddress : 0 x 0108 b it f unction t ype d efault d escription -o peration
xrt86l30 43 single t1/e1/j1 framer/liu combo rev. 1.0.1 5 yel(1) r/w 0 yellow alarm and multiframe yellow alarm generation these bits activate and deactivate the transmission of a yellow alarm. the decoding of these bits are explained as follows : 00, = disable the transmission of yellow alarm. 01 = in sf mode (or n mode), yellow alarm is transm itted as bit 2 = 0 (second msb) in all ds0 data channel. in t1dm mode, yellow is transmitted to the remote terminal by setting the outgoing y-bit to zero. in esf mode, follow the following scenario: 1. if yel[0] forms a pulse width shorter or equal t o the time required to transmit 255 pattern of 1111_1111_0000_0000 (eight ones followed by eight zeros) on the 4-kbit/s data link (m1-m12), the alarm is t ransmitted for 255 pat- terns. 2. if yel[0] is a pulse width longer than the time required to transmit 255 patterns, the alarm continues until tyel[0] goe s low. 3. a second yel[0] pulse during an alarm transmissi on resets the pat- tern counter and extends the alarm duration for anot her 255 patterns. 10 = in sf mode, yellow alarm is transmitted as a " 1" for the fs bit of frame 12, this is yellow alarm for j1 standard. in t1 dm mode, yellow is transmitted to the remote terminal by setting the outgoing y-bit to zero. in esf mode, yellow alarm is controlled by the duration o f yel[1]. this allows continuous alarms of any length. 11 = disable the transmission of yellow alarm. 4 yel(0) r/w 0 3 aisg(1) r/w 0 ais generation select these read/write bit-fields are used to configure t he channel to gener- ate and transmit an ais pattern, as described below . 00 = no ais alarm generated 01 = enable unframed ais alarm generation 10 = no ais alarm generated 11 = enable framed ais alarm generation 2 aisg(0) r/w 0 1 aisd(1) r/w 0 ais pattern detection select these read/write bit-fields are used to specify the type of ais pattern that the receive e1 framer block will detect as des cribed below. 00 = disabled 01 = unframed ais alarm detection 10 = ais16 detection 11 = unframed ais alarm detection 0 aisd(0) r/w 0 t able 17: a larm g eneration r egister -t1 m ode r egister 8 - t1 m ode a larm g eneration r egister (agr) h ex a ddress : 0 x 0108 b it f unction t ype d efault d escription -o peration
xrt86l30 44 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 18: s ynchronization mux r egister - e1 m ode r egister 9 - e1 m ode s ynchronization mux r egister (smr) h ex a ddress : 0 x 0109 b it f unction t ype d efault d escription -o peration 7-6 esrc[1:0] r/w 0 source for e bits these bits determine where the e bits should be ins erted from. 00 = transparent, inserted from the status of recei ver. 01 = 0. 10 = 1. 11 = data link. 5 reserved - - reserved 4 sync inv r/w 0 sync inversion select selects the direction of the transmit sync and mult isync signals. 0 = syncs are input if the css(1:0) bits of csr equ al 01 (txserclk input is selected as the timing reference for the tran smit section of the framer); otherwise syncs are outputs 1 = syncs are output if css(1:0) bits of csr equal 01 (txserclk input is selected as the timing reference for the tran smit section of the framer); otherwise syncs are inputs 3 dlsrc(1) r/w 0 data link source select specifies the source of the data link bits that wil l be inserted in the outbound e1 frames. 00 = txser input: transmit payload data input port will be source of data link bits. 01 = tx hdlc controller: transmit hdlc controller w ill generate either bos (bit oriented signaling) or mos (message ori ented signaling) messages which will be inserted into the data link bi t-fields in the outbound e1 frames. 10 = txoh_n input: transmit overhead data input por t will be the source of the data link bits. 11 = txser_n input: transmit payload data input por t will be the source of the data link bits. 2 dlsrc(0) r/w 0
xrt86l30 45 single t1/e1/j1 framer/liu combo rev. 1.0.1 1 crcsrc r/w 0 crc-4 bits source select this read/write bit-field is used to configure the transmit section of the channel to use either internal generation or th e txser_n input pin as the source of the crc-4 bits inserted into t he outbound frames. 0 = internally generated and inserted into e1 data stream internally. 1 = tx_ser input: transmit payload data input port will be source of crc-4 bits. n ote : this bit-field is ignored if crc multiframe alignme nt is disabled 0 fsrc r/w 0 framing alignment bits source select specifies source of the framing alignment bits, whi ch include fas alignment bits, multiframe alignment bits, e and a bits. 0 = internally generated and inserted into the outb ound e1 frames. 1 = txser_n input: transmit serial input port will be source of the fas bits, crc multiframe alignments and the e and a bits. t able 19: s ynchronization mux r egister - t1 m ode r egister 9 - t1 m ode s ynchronization mux r egister (smr) h ex a ddress : 0 x 0109 b it f unction t ype d efault d escription -o peration 7 reserved - - reserved 6 mframealign r/w 0 multiframe alignment this bit forces transmit frame counter aligns with the backplane mul- tiframe sync. 0 = the multiframe alignment is not enforced from b ackplane inter- face. 1 = the transmit multiframe is aligned with the inc oming backplane multiframe timing. 5 msync r/w o tx super frame sync this bit selects the transmit input sync signal fro m either the frame sync or superframe sync signals. 0 = sync input (txsync) is a frame sync. in 1.544m hz clock mode, txmsync is used, in other clock mode, txmsyn c is an input transmit clock. 1 = sync input is a superframe sync. 4 sync inv r/w 0 sync inversion select this bit changes the direction of transmit sync and multi-sync sig- nals. 0 = the syncs are inputs if css bits of csr equal t o 1, otherwise, syncs are outputs. 1 = the syncs are outputs if css bits of csr equal to 1, otherwise, syncs are inputs. t able 18: s ynchronization mux r egister - e1 m ode r egister 9 - e1 m ode s ynchronization mux r egister (smr) h ex a ddress : 0 x 0109 b it f unction t ype d efault d escription -o peration
xrt86l30 46 rev. 1.0.1 single t1/e1/j1 framer/liu combo 3 - 2 reserved - - reserved 1 crcsrc r/w 0 crc-6 bits source select this bit determines where the crc-6 bits should be inserted from. 0 = the crc-6 bits are generated and inserted inter nally. 1 = the crc-6 bits are passed through from the inp ut serial data only when iomux=0 and css < 3. n ote : this bit-field is ignored if crc multiframe alignme nt is disabled 0 fsrc r/w 0 framing alignment bits source select determines where the framing alignment bits should be inserted from. 0 = the framing alignment bits are inserted interna lly. 1 = the framing alignment bits are passed through f rom the input serial data only when iomux=0 and css < 3. t able 20: t ransmit s ignaling and d ata l ink s elect r egister - e1 m ode r egister 10 - e1 m ode t ransmit s ignaling and d ata l ink s elect r egister (tsdlsr) h ex a ddress :0 x 010a b it f unction t ype d efault d escription -o peration 7 txsa8enb r/w 0 specifies if the sa8 bit-field (bit 7 within timeslot 0 of non-fas frames) will be involved in the transport of data l ink information 0 = data link interface does not use sa8 bit-field. sa8 bit-field within each outbound non-fas frame will be set to 1. 1 = data link interface uses sa8 bit-field. n ote : this bit-field is only active when the txsigdl[2:0] bits within this register are set to 00x. this bit-field is ign ored in all other case. 6 txsa7enb r/w 0 specifies if the sa7 bit-field (bit 6 within timeslot 0 of non-fas frames) will be involved in the transport of data l ink information 0 = data link interface does not use sa7 bit-field. sa7 bit-field within each outbound non-fas frame will be set to 1. 1 = data link interface uses sa7 bit-field. n ote : this bit-field is only active when the txsigdl[2:0] bits within this register are set to 00x. this bit-field is ign ored in all other cases. 5 txsa6enb r/w 0 specifies if the sa6 bit-field (bit 5 within timeslot 0 of non-fas frames) will be involved in the transport of data l ink information 0 = data link interface does not use sa6 bit-field. sa6 bit-field within each outbound non-fas frame will be set to 1. 1 = data link interface uses sa6 bit-field. n ote : this bit-field is only active when the txsigdl[2:0] bits within this register are set to 00x. this bit-field is ign ored in all other case. t able 19: s ynchronization mux r egister - t1 m ode r egister 9 - t1 m ode s ynchronization mux r egister (smr) h ex a ddress : 0 x 0109 b it f unction t ype d efault d escription -o peration
xrt86l30 47 single t1/e1/j1 framer/liu combo rev. 1.0.1 4 txsa5enb r/w 0 specifies if the sa5 bit-field (bit 4 within timeslot 0 of non-fas frames) will be involved in the transport of data l ink information 0 = data link interface does not use sa5 bit-field. sa5 bit-field within each outbound non-fas frame will be set to 1. 1 = data link interface uses sa5 bit-field. n ote : this bit-field is only active when the txsigdl[2:0] bits within this register are set to 00x. this bit-field is ign ored in all other case. 3 txsa4enb r/w 0 specifies if the sa4 bit-field (bit 3 within timeslot 0 of non-fas frames) will be involved in the transport of data l ink information 0 = data link interface does not use sa4 bit-field. sa4 bit-field within each outbound non-fas frame will be set to 1. 1 = data link interface uses sa4 bit-field. n ote : this bit-field is only active when the txsigdl[2:0] bits within this register are set to 00x. this bit-field is ign ored in all other case. 2 txsigdl(2) r/w 0 these three read/write bits are used to specify the type of data that is to be transported via d/e channel, national bits in timeslot 0 of the non-fas frames, and timeslot 16 in the outbound fra mes. d/e channel 0xx = fractional input 1xx = serial signaling input national bits (sa4-8 ) 000 = data link data inserted into national bits 001 = data link data inserted into national bits 010 = national bits forced to 1, not used to carry data link data 011 = none (forced to 1) 1xx = data link data inserted into national bits timeslot 16 000 = timeslot 16 is taken directly from pcm 001 = cas signaling bits a,b,c,d (per time slot) 010 = ccs signaling bits a,b,c,d 011 = cas signaling bits a,b,c,d (per time slot) 1xx = timeslot 16 is taken directly from pcm 1 txsigdl(1) r/w 0 0 txsigdl(0) r/w 0 t able 21: t ransmit s ignaling and d ata l ink s elect r egister - t1 m ode r egister 10 - t1 m ode t ransmit s ignaling and d ata l ink s elect r egister (tsdlsr) h ex a ddress :0 x 010a b it f unction t ype d efault d escription -o peration 7 reserved - - reserved 6 reserved - - reserved t able 20: t ransmit s ignaling and d ata l ink s elect r egister - e1 m ode r egister 10 - e1 m ode t ransmit s ignaling and d ata l ink s elect r egister (tsdlsr) h ex a ddress :0 x 010a b it f unction t ype d efault d escription -o peration
xrt86l30 48 rev. 1.0.1 single t1/e1/j1 framer/liu combo 5 txdlbw[1] r/w r/w 00 data link bandwidth 00 = fdl is a 4khz data link channel 01 = fdl is a 2khz data link channel carried by odd framing bits (1,5,9....) 10 = fdl is a 2khz data link channel carried by eve n framing bits(3,7,11...) 4 txdlbw[0] r/w 0 3 txde[1] r/w 0 de select 00 = the d/e time slots are inserted from txser. 01 = the d/e time slots are inserted from the lapd controller. 10 = the d/e time slots are inserted from the seria l signaling input. 11 = the d/e time slots are inserted from the fract ional input. 2 txde[0] r/w 0 1 txdl[1] r/w 0 dl select 00 = lapd controller/slc96 buffer. the data link bi ts are inserted from the lapd controller. (lapd1 is the only contro ller that can be used to transport lapd messages through the data li nk bits) 01 = serial input. the data link bits are inserted from serial data input. 10 = overhead input. the data link bits are inserte d from overhead input. 11 = none (forced to 1). the data link bits are for ced to 1. 0 txdl[0] r/w 0 t able 22: f raming c ontrol r egister e1 m ode r egister 11 -- e1 m ode f raming c ontrol r egister (fcr) h ex a ddress : 0 x 010b b it f unction t ype d efault d escription -o peration 7 rsync r/w 0 force re-synchronization a 0 to 1 transition in this bit-field forces the re ceive e1 framer to restart the synchronization process. this bit field is automatically cleared (set to 0) after frame synchronization is r eached. 6 casc(1) r/w 0 loss of cas multiframe alignment criter ia select these two read/write bits are used to select the lo ss of cas multi- frame alignment declaration criteria. the relations hip between the state of these two bit fields and the corresponding loss of cas multi- frame is presented below. 00 = two consecutive cas multi-frames with multifra me alignment signal (mas) errors 01 = three consecutive cas multi-frames with mas er rors 10 = four consecutive cas multi-frames with mas err ors 11 = eight consecutive cas multi-frames with mas er rors n ote : these bits are only active if channel associated si gnaling is used. 5 casc(0) r/w 0 t able 21: t ransmit s ignaling and d ata l ink s elect r egister - t1 m ode r egister 10 - t1 m ode t ransmit s ignaling and d ata l ink s elect r egister (tsdlsr) h ex a ddress :0 x 010a b it f unction t ype d efault d escription -o peration
xrt86l30 49 single t1/e1/j1 framer/liu combo rev. 1.0.1 4 crcc(1) r/w 0 loss of crc-4 multiframe alignment crit eria select selects criteria for loss of crc-4 multiframe align ment. 00 = four consecutive crc multiframe alignment sign als have been received in error 01 = two consecutive crc multiframe alignment signa ls have been received in error 10 = eight consecutive crc multiframe alignment sig nals have been received in error 11 = 915 or more crc-4 errors have been detected in one second. n ote : these bit-fields are ignored if crc multiframe alig nment has been disabled. 3 crcc(0) r/w 0 2 fasc(2) r/w 0 loss of fas alignment criteria select these three read/write bits are used to select loss of fas frame declaration criteria. the relationship between the state of these bits and the corresponding loss of fas frame declaration is presented below. 000 = illegal - do not use 001 = 1 errored fas pattern 010 = 2 consecutive errored fas patterns 011 = 3 consecutive errored fas patterns 100 = 4 consecutive errored fas patterns 101 = 5 consecutive errored fas patterns 110 = 6 consecutive errored fas patterns 111 = 7 consecutive errored fas patterns 1 fasc(1) r/w 1 0 fasc(0) r/w 1 t able 23: f raming c ontrol r egister t1 m ode r egister 11 -- t1 m ode f raming c ontrol r egister (fcr) h ex a ddress : 0 x 010b b it f unction t ype d efault d escription -o peration 7 rsync r/w 0 force re-synchronization a 0 to 1 transition in this bit-field forces the re ceive ds1 framer to restart the synchronization process. this bit field is automatically cleared (set to 0) after frame synchronization is r eached. 6 crcenb/ oneonly r/w 0 sync with crc verification in esf. (assuming only one ft sync can- didate exists.) 0 = no crc match test 1 = include crc match test as part of synchronizati on criteria. 5 tolr[2] r/w 0 tolerance bits [2:0] the tolerance (tolr) and range (rang) form the crit eria for loss of frame alignment. a loss of frame is declared if th ere is tolr out of rang errors in the framing pattern. the recommend ed tolr value is 2. n ote : a 0 value for tolr is internally blocked. a tolr value must be specified. 4 tolr[1] r/w 1 3 tolr[0] r/w 0 t able 22: f raming c ontrol r egister e1 m ode r egister 11 -- e1 m ode f raming c ontrol r egister (fcr) h ex a ddress : 0 x 010b b it f unction t ype d efault d escription -o peration
xrt86l30 50 rev. 1.0.1 single t1/e1/j1 framer/liu combo 2 rang[2] r/w 1 range bits [2:0] the tolerance (tolr) and range (rang) form the crit eria for loss of frame alignment. a loss of frame is declared if th ere is tolr out of rang errors in the framing pattern. the recommend ed rang value is 5. n ote : a 0 value for rang is internally blocked. a rang value must be specified. 1 rang[1] r/w 0 0 rang[0] r/w 1 t able 24: r eceive s ignaling & d ata l ink s elect r egister - e1 m ode r egister 12 - e1 m ode r eceive s ignaling & d ata l ink s elect r egister (rs&dlsr) h ex a ddress : 0 x 010c b it f unction t ype d efault d escription -o peration 7 rxsa8enb r/w 0 this read/write bit is used to specify whether or not data link infor- mation will be transported via national bit sa8 (bi t 7 within timeslot 0 of non-fas frames) 0 = sa8 does not carry data link information 1 = sa8 carries data link information n ote : this bit-field is valid only if the rxsigdl[2:0] = 000 or 001. (the national bits have been configured to carry da ta link bits). 6 rxsa7enb r/w 0 this read/write bit is used to specify whether or not data link infor- mation will be transported via national bit sa7 (bi t 6 within timeslot 0 of non-fas frames) 0 = sa7 does not carry data link information 1 = sa7 carries data link information n ote : this bit-field is valid only if the rxsigdl[2:0] = 000 or 001. (the national bits have been configured to carry da ta link bits). 5 rxsa6enb r/w 0 this read/write bit is used to specify whether or not data link infor- mation will be transported via national bit sa6 (bi t 5 within timeslot 0 of non-fas frames) 0 = sa6 does not carry data link information 1 = sa6 carries data link information n ote : this bit-field is valid only if the rxsigdl[2:0] = 000 or 001. (the national bits have been configured to carry da ta link bits). 4 rxsa5enb r/w 0 this read/write bit is used to specify whether or not data link infor- mation will be transported via national bit sa5 (bi t 4 within timeslot 0 of non-fas frames) 0 = sa5 does not carry data link information 1 = sa5 carries data link information n ote : this bit-field is valid only if the rxsigdl[2:0] = 000 or 001. (the national bits have been configured to carry da ta link bits). t able 23: f raming c ontrol r egister t1 m ode r egister 11 -- t1 m ode f raming c ontrol r egister (fcr) h ex a ddress : 0 x 010b b it f unction t ype d efault d escription -o peration
xrt86l30 51 single t1/e1/j1 framer/liu combo rev. 1.0.1 3 rxsa4enb r/w 0 this read/write bit is used to specify whether or not data link infor- mation will be transported via national bit sa4 (bi t 3 within timeslot 0 of non-fas frames) 0 = sa4 does not carry data link information 1 = sa4 carries data link information n ote : this bit-field is valid only if the rxsigdl[2:0] = 000 or 001. (if the national bits have been configured to carry data link bits). 2 rxsigdl(2) r/w 0 these three read/write bits are used to specify the type of data that is to be extracted via d/e channel, national bits i n timeslot 0 of the non-fas frames, and timeslot 16 in the outbound fra mes. d/e channel 0xx = fractional output 1xx = serial signaling output national bits (sa4-8 ) 000 = data link data extracted from national bits 001 = data link data extracted from national bits 010 = national bits forced to 1, not used to carry data link data 011 = none (forced to 1) 1xx = data link data extracted from national bits timeslot 16 000 = timeslot 16 is taken directly from pcm 001 = cas signaling bits a,b,c,d (per time slot) 010 = ccs signaling bits a,b,c,d 011 = cas signaling bits a,b,c,d (per time slot) 1xx = timeslot 16 is taken directly from pcm 1 rxsigdl(1) r/w 0 0 rxsigdl(0) r/w 0 t able 25: r eceive s ignaling & d ata l ink s elect r egister (rs&dlsr) t1 m ode r egister 12 - t1 m ode r eceive s ignaling & d ata l ink s elect r egister (rs&dlsr) h ex a ddress : 0 x 010c b it f unction t ype d efault d escription -o peration 7 reserved - - reserved 6 reserved - - reserved 5 rxdlbw[1] r/w 0 data link bandwidth 00 = fdl is a 4khz data link channel. 01 = fdl is a 2khz data link channel carried by old framing bits(1,5,9,....). 10 = fdl is a 2khz data link channel carried by eve n framing bits(3,7,11,....). 4 rxdlbw[0] r/w 0 3 rxde[1] r/w 0 de select 00 = the d/e time slots are output to rxser. 01 = the d/e time slots are output to the lapd cont roller. 10 = the d/e time slots are output to the serial si gnaling output. 11 = the d/e time slots are output to the fractiona l output. 2 rxde[0] r/w 0 t able 24: r eceive s ignaling & d ata l ink s elect r egister - e1 m ode r egister 12 - e1 m ode r eceive s ignaling & d ata l ink s elect r egister (rs&dlsr) h ex a ddress : 0 x 010c b it f unction t ype d efault d escription -o peration
xrt86l30 52 rev. 1.0.1 single t1/e1/j1 framer/liu combo 1 rxdl[1] r/w 0 dl select 00 = lapd controller/slc96 buffer. the data link bi ts are extracted from the lapd controller. (lapd1 is the only contro ller that can be used to extract lapd messages through the data link bits) 01 = serial input. the data link bits are extracted to the serial data out- put. 10 = overhead input. the data link bits are extract ed to the overhead output. 11 = none (forced to 1). the data link bits are for ced to 1. 0 rxdl[0] r/w 0 t able 26: s ignaling c hange r egister 0 - t1 m ode r egister 13 - t1/e1 m ode s ignaling c hange r egister 0 (scr 0) h ex a ddress : 0 x 010d b it f unction t ype d efault d escription -o peration 7 ch. 0 rur 0 these reset upon read bits indicate wheth er the signaling data asso- ciated with channels 0-7 has changed since the last read of this regis- ter. 0 = signaling data has not changed since last read of register 1 = signaling data has changed since last read of r egister n ote : for e1, ch. 0 is not applicable since it carries fa s and national bits in alternating frames. this register is only relevant if the framing channel is using channel associated signali ng 6 ch. 1 rur 0 5 ch.2 rur 0 4 ch.3 rur 0 3 ch.4 rur 0 2 ch.5 rur 0 1 ch.6 rur 0 0 ch.7 rur 0 t able 27: s ignaling c hange r egister 1 r egister 14 t1/e1 m ode s ignaling c hange r egister 1 (scr 1) h ex a ddress : 0 x 010e b it f unction t ype d efault d escription -o peration 7 ch.8 rur 0 these reset upon read bits indicate whethe r the signaling data asso- ciated with channels 8-15 has changed since the las t read of this regis- ter. 0 = signaling data has not changed since last read of register 1 = signaling data has changed since last read of r egister n ote : this register is only relevant if the framing chann el is using channel associated signaling 6 ch.9 rur 0 5 ch.10 rur 0 4 ch.11 rur 0 3 ch.12 rur 0 2 ch.13 rur 0 1 ch.14 rur 0 0 ch.15 rur 0 t able 25: r eceive s ignaling & d ata l ink s elect r egister (rs&dlsr) t1 m ode r egister 12 - t1 m ode r eceive s ignaling & d ata l ink s elect r egister (rs&dlsr) h ex a ddress : 0 x 010c b it f unction t ype d efault d escription -o peration
xrt86l30 53 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 28: s ignaling c hange r egister 2 r egister 15 t1/e1 m ode s ignaling c hange r egister 2 (scr 2) h ex a ddress : 0 x 010f b it f unction t ype d efault d escription -o peration 7 ch.16 rur 0 these reset upon read bits indicate wheth er the signaling data asso- ciated with channels 16-23 has changed since the la st read of this reg- ister. 0 = signaling data has not changed since last read of register 1 = signaling data has changed since last read of r egister n ote : this register is only relevant if the framing chann el is using channel associated signaling 6 ch.17 rur 0 5 ch.18 rur 0 4 ch.19 rur 0 3 ch.20 rur 0 2 ch.21 rur 0 1 ch.22 rur 0 0 ch.23 rur 0 t able 29: s ignaling c hange r egister 3 r egister 16 - e1 m ode s ignaling c hange r egister 3 (scr 3) h ex a ddress : 0 x 0110 b it f unction t ype d efault d escription -o peration 7 ch.24 rur 0 these reset upon read bits indicate wheth er the signaling data associated with channels 24-31 has changed since th e last read of this register. 0 = signaling data has not changed since last read of register 1 = signaling data has changed since last read of r egister n ote : this register is only relevant if the framing chann el is using channel associated signaling 6 ch.25 rur 0 5 ch.26 rur 0 4 ch.27 rur 0 3 ch.28 rur 0 2 ch.29 rur 0 1 ch.30 rur 0 0 ch.31 rur 0 t able 30: r eceive n ational b its r egister r egister 17 r eceive n ational b its r egister (rnbr) h ex a ddress : 0 x 0111 b it f unction t ype d efault d escription -o peration 7 si_fas ro x received international bit - fas frame this read only bit-field contains the value of the international bit in the most recently received fas frame 6 si_nonfas ro x received international bit - non fas f rame this read only bit-field contains the value of the international bit in the most recently received non-fas frame 5 r_alarm ro x received fas yellow alarm this read only bit-field contains the value in the remote alarm bit- field (frame yellow alarm) within the non-fas frame .
xrt86l30 54 rev. 1.0.1 single t1/e1/j1 framer/liu combo n ote : the value of bits [3:0] within this register only h ave meaning if the framer is using channel associat ed signaling. 4 sa4 ro x received national bits these read only bit-fields contain the values of th e national bits within the most recently received non-fas frame. 3 sa5 ro x 2 sa6 ro x 1 sa7 ro x 0 sa8 ro x t able 31: r eceive e xtra b its r egister r egister 18 r eceive e xtra b its r egister (rebr) h ex a ddress : 0 x 0112 b it f unction t ype d efault d escription -o peration 7 if detection ro 0 in frame detection (ds1/e1) this register bit is used to indicate whether the r eceive framer is in frame or out of frame. 0 = out of frame 1 = in frame 6-4 reserved - - reserved 3 ex1 ro x extra bit 1 corresponds to value in bit 5 within timeslot 16 of frame 0 of the signaling multiframe 2 alarmfe ro x cas multi-frame yellow alarm corresponds to value in bit 6(cas multiframe yellow alarm) within timeslot 16 of frame 0 of the signaling multiframe. 0 = remote e1 transmitting terminal is not sending cas multiframe yel- low alarm 1 = remote e1 transmitting terminal is sending cas multiframe yellow alarm 1 ex2 ro x extra bit 2 corresponds to value in bit 7 within timeslot 16 of frame 0 of the signaling multiframe 0 ex3 ro x extra bit 3 corresponds to value in bit 8 within timeslot 16 of frame 0 of the signaling multiframe t able 30: r eceive n ational b its r egister r egister 17 r eceive n ational b its r egister (rnbr) h ex a ddress : 0 x 0111 b it f unction t ype d efault d escription -o peration
xrt86l30 55 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 32: d ata l ink c ontrol r egister r egister 19 d ata l ink c ontrol r egister 1 (dlcr1) h ex a ddress : 0 x 0113 b it f unction t ype d efault d escription -o peration 7 slc-96 r/w 0 slc ? 96 enable, 6 bit for esf if slc ? 96 framing is selected, setting this bit high will enable slc ? 96 data link transmission; otherwise, the regular s f framing bits are transmitted. in esf framing mode, setting this bit high will cau se facility data link to transmit/receive slc ? 96-like message. 6 mosa r/w 0 mos abort enable/disable select this read/write bit-field is used to configure the transmit hdlc1 controller to automatically transmit an abort seque nce anytime it transitions from the mos mode to the bos mode. 0 = transmit hdlc1 controller inserts an mos abort sequence if the mos message is interrupted 1 = prevents transmit hdlc1 controller from inserti ng an mos abort sequence. 5 rx_fcs_dis r/w 0 receive fcs verification disable enables/disables receive hdlc1 controllers computa tion and verification of the fcs value in the incoming lapd message frame 0 = verifies fcs value of each mos frame. 1 = does not verify fcs value of each mos frame. 4 autorx r/w 0 auto receive lapd message configures the rx hdlc1 controller to discard any i ncoming lapd message frame that exactly match which is currently stored in the rx hdlc1 buffer. 0 = disabled 1 = enables this feature. 3 tx_abort r/w 0 transmit abort configures the tx hdlc1 controller to transmit an a bort sequence (string of 7 or more consecutive 1s) to t he remote termi- nal. 0 = tx hdlc1 controller operates normally 1 = tx hdlc1 controller inserts an abort sequence i nto the data link channel. 2 tx_idle r/w 0 transmit idle (flag sequence byte) configures the tx hdlc1 controller to transmit a st ring of flag sequence octets (0x7e) in the data link channel to the remote ter- minal. 0 = tx hdlc1 controller resumes transmitting data t o the remote terminal 1 = tx hdlc1 controller transmits a string of flag sequence bytes. n ote : this bit-field is ignored if the tx hdlc1 controlle r is operating in the bos mode - bit-field 0(mos/bos) wi thin this register is set to 0.
xrt86l30 56 rev. 1.0.1 single t1/e1/j1 framer/liu combo 1 tx_fcs_en r/w 0 transmit lapd message with fcs configure hdlc1 controller to include/not include f cs octets in the outbound lapd message frames. 0 = does not include fcs octets into the outbound l apd message frame. 1 = inserts fcs octets into the outbound lapd messa ge frame. n ote : this bit-field is ignored if the transmit hdlc1 con troller has been configured to operate in the bos mode. 0 mos/bos r/w 0 message oriented signaling/bit oriented signali ng select specifies whether the txrx hdlc1 controller will be transmitting and receiving lapd message frames (mos) or bit orie nted signal (bos) messages. 0 = tx/rx hdlc1 controller transmits and receives b os messages. 1 = tx/rx hdlc1 controller transmits and receives m os mes- sages. t able 33: t ransmit d ata l ink b yte c ount r egister r egister 20 t ransmit d ata l ink b yte c ount r egister 1 (tdlbcr1) h ex a ddress : 0 x 0114 b it f unction t ype d efault d escription -o peration 7 bufaval//bufsel r/w 0 transmit hdlc1 buffer available /buffer select specifies which of the two tx hdlc1 buffers that th e tx hdlc1 controller should read from to generate the next ou tbound hdlc1 message. 0 = transmits message data residing in tx hdlc1 buf fer 0. 1 = transmits message data residing in tx hdlc1 buf fer 1. n ote : if one of these tx hdlc1 buffers contain a message which has yet to be completely read-in and processed for transmission by the tx hdlc1 controller, then this bit-field will automatically reflect the value corresponding to the available buffer. changing this bit-field to the in -use buffer is not permitted. 6 tdlbc6 r/w 0 transmit hdlc1 message - byte count depends on whether an mos or bos message is being t ransmitted to the remote terminal equipment if bos message is being transmitted : these bit fields contain the number of repetitions the bos message must be trans mitted before the tx hdlc1 controller generates the txeot interru pt and halts transmission. if these fields are set to 00000000, then the bos mes- sage will be transmitted for an indefinite number o f times. if mos message is being transmitted: these bit fields contain the length, in number of octets, of the message to be t ransmitted. 5 tdlbc5 r/w 0 4 tdlbc4 r/w 0 3 tdlbc3 r/w 0 2 tdlbc2 r/w 0 1 tdlbc1 r/w 0 0 tdlbc0 r/w 0 t able 32: d ata l ink c ontrol r egister r egister 19 d ata l ink c ontrol r egister 1 (dlcr1) h ex a ddress : 0 x 0113 b it f unction t ype d efault d escription -o peration
xrt86l30 57 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 34: r eceive d ata l ink b yte c ount r egister r egister 21 r eceive d ata l ink b yte c ount r egister 1 (rdlbcr1) h ex a ddress : 0 x 0115 b it f unction t ype d efault d escription -o peration 7 rbufptr r/w 0 receive hdlc1 buffer-pointer identifies which rxhdlc1 buffer contains the newly received hdlc1 message. 0 = hdlc1 message is stored in rx hdlc1 buffer 0. 1 = hdlc1 message is stored in rx hdlc1 buffer 1. 6 rdlbc6 r/w 0 re ceive hdlc message - byte count in mos mode these seven bit-fields contain the size in bytes of the hdlc1 mes- sage that has been extracted and written into the r x hdlc1 buffer. in bos mode these bits should be set to the value of the messag e repetitions before each receive interrupt. if they are set to 0, no rxeot inter- rupt will be generated. 5 rdlbc5 r/w 0 4 rdlbc4 r/w 0 3 rdlbc3 r/w 0 2 rdlbc2 r/w 0 1 rdlbc1 r/w 0 0 rdlbc0 r/w 0 t able 35: s lip b uffer c ontrol r egister r egister 22 s lip b uffer c ontrol r egister (sbcr) h ex a ddress : 0 x 0116 b it f unction t ype d efault d escription -o peration 7 txsb_isfifo r/w 0 selects slip buffer as a fifo for a ll clock modes while txclk and txserclk are synced. 0 = buffer acts as slip buffer if enabled. 1 = buffer acts as a fifo. the data latency is dic tated by fifo latency. 6-5 reserved - - reserved 4 sb_forcesf r/w 0 force signaling freeze setting this bit high stops further signal updati ng until this bit is cleared. 1 = signaling array is not updated. 0 = signaling array is updated only if sb_enb[1:0] = 01 or 10 3 sb_sfenb r/w 0 signal freeze enable this bit enables signaling freeze for one multifram e after buffer slip- ping. 1 = signaling freeze is enabled. 0 = signaling freeze is disabled. 2 sb_sdir r/w 1 slip buffer (rxsync) direction selec t allows rxsync output pin to be an input or an outpu t. 0 = rxsync is an output pin 1 = rxsync is an input pin
xrt86l30 58 rev. 1.0.1 single t1/e1/j1 framer/liu combo 1 sb_enb(1) r/w 0 slip buffer mode select selects mode of operation of slip buffer. 00 = buffer is bypassed and rxsync and rxserclk are outputs. 01 = elastic store slip buffer enabled. rxserclk is an input. 10 = buffer acts as fifo data latency dictated by t he setting within the fifo latency register. rxserclk is an input. 11 = buffer is bypassed. rxsync and rxserclk are o utputs. 0 sb_enb(0) r/w 0 t able 36: fifo l atency r egister r egister 23 fifo l atency r egister (ffolr) h ex a ddress : 0 x 0117 b it f unction t ype d efault d escription -o peration 7-5 reserved - - reserved 4-0 latency r/w 0 sets the distance between slip buffer read and slip buffer write point- ers in fifo mode. t able 37: dma 0 (w rite ) c onfiguration r egister r egister 24 dma 0 w rite c onfiguration r egister (d 0 wcr) h ex a ddress : 0 x 0118 b it f unction t ype d efault d escription -o peration 7 dma0 rst r/w 0 dma_0 reset resets transmit dma 0 channel. 0 = normal operation. 1 = a zero to one transition resets dma channel_0. 6 dma0 enb r/w 0 dma_0 enable enables dma_0 interface. 0 = disables dma_0 interface 1 = enables dma_0 interface 5 wr type r/w 0 write type select selects function of wr signal. 0 = wr functions as direction signal (indicates whether t he current bus cycle is a read or write operation) and rd functions as a data strobe signal. 1 = wr functions as a write strobe signal and rd functions as con- figured in the dma 1 configuration register. 4 - 3 reserved - - reserved t able 35: s lip b uffer c ontrol r egister r egister 22 s lip b uffer c ontrol r egister (sbcr) h ex a ddress : 0 x 0116 b it f unction t ype d efault d escription -o peration
xrt86l30 59 single t1/e1/j1 framer/liu combo rev. 1.0.1 2 dma0_chan(2) r/w 0 channel select selects which channel, within the chip, is to use t he dma_0 (write) interface. 000 = channel 0 001 = channel 1 001 = channel 2 011 = channel 3 100 = channel 4 101 = channel 5 110 = channel 6 111 = channel 7 1 dma0_chan(1) r/w 0 0 dma0_chan(0) r/w 0 t able 38: dma 1 (r ead ) c onfiguration r egister r egister 25 dma 1 (r ead ) c onfiguration r egister (d1cr) h ex a ddress : 0 x 0119 b it f unction t ype d efault d escription -o peration 7-6 reserved - - reserved 7 dma1 rst r/w 0 dma_1 reset resets the dma 1 channel 0 = normal operation. 1 = a zero to one transition resets dma channel. 6 dma1 enb r/w 0 dma1_enb enables dma_1 interface 0 = disables dma_1 interface 1 = enables dma_1 interface 5 rd type r/w 0 selects the function of prd_l signal. 0 = rd functions as a read strobe signal 11 = rd acts as a direction signal, wr works as a data strobe. 4 - 3 reserved - - reserved 2 dma1_chan(2) r/w 0 channel select selects which channel, within the chip, is to use t he dma_1 inter- face. 000 = channel 0 001 = channel 1 001 = channel 2 011 = channel 3 100 = channel 4 101 = channel 5 110 = channel 6 111 = channel 7 1 dma1_chan(1) r/w 0 0 dma1_chan(0) r/w 0 t able 37: dma 0 (w rite ) c onfiguration r egister r egister 24 dma 0 w rite c onfiguration r egister (d 0 wcr) h ex a ddress : 0 x 0118 b it f unction t ype d efault d escription -o peration
xrt86l30 60 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 39: i nterrupt c ontrol r egister r egister 26 i nterrupt c ontrol r egister (icr) h ex a ddress : 0 x 011a b it f unction t ype d efault d escription -o peration 7-3 reserved - - reserved 2 int_wc_rur r/w 0 interrupt write-to-clear or reset-up on-read select configures interrupt status bits to either reset up on read or write- to-clear 0=interrupt status bit rur 1=interrupt status bit write-to-clear 1 enbclr r/w 0 interrupt enable auto clear 0=interrupt enable bits are not cleared after statu s reading 1=interrupt enable bits are cleared after status re ading 0 intrup_enb r/w 0 interrupt enable for framer_n enables framer n for interrupt generation. 0 = disables corresponding framer block for interru pt generation 1 = enables corresponding framer block for interrup t generation t able 40: lapd s elect r egister r egister 27 lapd s elect r egister (lapdsr) h ex a ddress : 0 x 011b b it f unction t ype d efault d escription -o peration [7:2] reserved - - these bits are reserved [1:0] lapdsel r/w 0 lapd select bits [1:0] determine which hdlc controller has acce ss to the read/ write registers 0x0600 and 0x0700 for storing or ex tracting lapd messages. 00 = hdlc controller 1 01 = hdlc controller 2 10 = hdlc controller 3 11 = hdlc controller 1
xrt86l30 61 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 41: c ustomer i nstallation a larm g eneration r egister r egister 28 - t1 c ustomer i nstallation a larm g eneration r egister (ciagr) h ex a ddress : 0 x 011c b it f unction t ype d efault d escription -o peration [7:4] reserved - - these bits are reserved [3:2] ciag r/w 0 ci alarm transmit (only in esf) alarm indication signal-customer installation (ais- ci) and remote alarm indication-customer installation (rai-ci) are intended for use in a network to differentiate between an issue with in the network or the ci. ais-ci is an all ones signal with an embed ded signature of 01111100 11111111 right-to left which recurs at 386 bit intervals in- the ds-1 signal. 00 = no ci alarm generation 01 = enable unframed ais-ci alarm generation 10 = enable rai-ci generation 11 = no ci alarm generation [1:0] ciad r/w 0 ci alarm detect (only in esf) 00 = ci alarm detection is disabled 01 = enable unframed ais-ci alarm detection 10 = enable rai-ci detection 11 = ci alarm detection is disabled t able 42: p erformance r eport c ontrol r egister r egister 29 - t1 p erformance r eport c ontrol (prcr) h ex a ddress : 0 x 011d b it f unction t ype d efault d escription -o peration [7:2] reserved - - these bits are reserved [1:0] apcr r/w 0 automatic performance control/response report these bits automatically generates a summary report of the pmon status so that it can be inserted into an out going lapd message. 00 = no performance report issued 01 = single performance report issued when a write of 00 follows by a write of 01 10 = automatically issues a performance report ever y one second 11 = no performance report issued
xrt86l30 62 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 43: g apped c lock c ontrol r egister r egister 30 - t1/e1 g apped c lock c ontrol r egister (gccr) h ex a ddress : 0 x 011e b it f unction t ype d efault d escription -o peration 7 froutclk r/w 0 framer output clock reference by default, the output clock reference on t1oscclk and e1oscclk output pins is 1.544mhz/2.048mhz respectiv ely. by setting this bit to a 1, the output clock referen ce is 49.408mhz/ 65.536mhz for t1/e1 respectively. 0 = standard t1/e1 rate 1 = high-speed rate [6:2] reserved - - these bits are reserved 1 txgccr r/w 0 transmit gapped clock interface this bit is used to select a gapped clock interface operating at 2.048mbit/s in ds-1 mode. in this application, 63 gaps (missing data) are inserted so that the overall bit rate is reduced to 1.544mbit/ s. (in this mode, txmsync is used as the 2.048mhz gapped clock input. txser is used as the 2.048mhz gapped data i nput. txserclk must be 1.544mhz.) 0 = disabled 1 = transmit gapped clock for the transmit path 0 rxgccr r/w 0 receive gapped clock interface this bit is used to select a gapped clock interface operating at 2.048mbit/s in ds-1 mode. in this application, 63 gaps (missing data) are inserted so that the overall bit rate is reduced to 1.544mbit/ s. (in this mode, rxserclk should be configured as an input so that a 2.048mhz gapped clock can be applied to the framer block. rxser is used as the 2.048mhz gapped data output. the posi- tion of the gaps will be determined by the gaps pla ced in rxser- clk by the user.) 0 = disabled 1 = receive gapped clock for the receive path t able 44: g apped c lock c ontrol r egister r egister 31 - t1/e1 m ultiplexed () h ex a ddress : 0 x 011f b it f unction t ype d efault d escription -o peration 7:2 reserved r/w - reserved 1:0 mhsccr[1:0] r/w 00 multiplexed high-speed channel c ontrol these bits are used to select which channel (the ch annel position can be chosen from 1 of 4 different time slots) wit hin the high-speed serial data is to be processed by the framer. the other three chan- nels will be dont care bits, since this is a singl e channel device. this allows the xrt86l30 to be compatible with high -speed modes such as hmvip/h.100, etc. 00 = channel 0 01 = channel 1 10 = channel 2 11 = channel 3
xrt86l30 63 single t1/e1/j1 framer/liu combo rev. 1.0.1 registers 0x1b thru 0x1f unused. t able 45: t ransmit i nterface c ontrol r egister - e1 m ode r egister 32 - e1 m ode t ransmit i nterface c ontrol r egister (ticr) h ex a ddress :0 x 0120 b it f unction t ype d efault d escription -o peration 7 txsyncfrd r/w 0 tx synchronous fraction data interfac e 0 = fractional data is clocked into the chip using txchclk 1 = fractional data is clocked in to the chip using txserclk (ungapped). txchn[4:0] still indicates the time slot numb er if txfr2048 is not 1, tximode[1:0] = 00, and txmuxen = 0. txchclk i s used as frac- tional data enable. 6 reserved - - reserved 5 txplclkenb r/w 0 tx payload clock enable 1 = txserclk will output tx clock with oh bit perio d blocked in 2.048hz clock output mode. txsync is low r/w 0 txsync is low in h.100 and hmvip mode 0 = txsync is active low 1 = txsync is active high 4 txfr2048 r/w 0 if txmuxen = 0 and tximode[1:0] = 00 0 = txchn[4:0] outputs the channel number as usual. 1 = txchn[0]/txsig inputs signaling information and txchn[1]/txfrtd will input fractional channel data in 2.048 mbit mode. note; this bit has no effect while either txmuxen = 1 or tximode[1:0] = 00, txchn[4:0] signals input txsig and fractiona l data. 3 txiclkinv r/w 0 clock inversion 0 = data transition happens on rising edge of the t ransmit clocks. 1 = data transition happens on falling edge of the transmit clocks. 2 txmuxen r/w 0 mux enable 0 = no channel multiplexing. 1 = four channels are multiplexed in single serial stream.
xrt86l30 64 rev. 1.0.1 single t1/e1/j1 framer/liu combo 1 tximode[1] r/w 0 tx interface mode selection this mode selection determines the interface speed. when txmuxen = 0, 00 = transmit interface is taking data at a rate o f 2.048mbit/s. 01 = transmit interface is taking data at a rate o f 2.048mbit/s. 10 = transmit interface is taking data at a rate o f 4.096mbit/s. 11 = transmit interface is taking data at a rate o f 8.192mbit/s. when txmuxen = 1, 00 = reserved 01 = transmit interface is taking data at a rate of 16.384mbit/s from channel 0 and bit-demultiplexing into 4 channels fr om to the liu out- puts on channels 0 through 3. the txsync pulse rem ains high dur- ing the first bit of each e1 frame. 10 = transmit interface is taking data at a rate of 16.384mbit/s from channel 0 and byte-demultiplexing into 4 channels f rom to the liu out- puts on channels 0 through 3 (hmvip mode). the txs ync pulse remains high during the last two bits of the prev ious e1 frame and the first two bits of the current e1 frame. 11 = transmit interface is taking data at a rate of 16.384mbit/s from channel 0 and byte-demultiplexing into 4 channels f rom to the liu out- puts on channels 0 through 3 (h.100 mode). the txs ync pulse remains high during the last bit of the previous e1 frame and the first bit of the current e1 frame. n ote : channel 4 is de-multiplexed into the liu outputs at channel 4 through 7. 0 tximode[0] r/w 0 t able 46: t ransmit i nterface c ontrol r egister - t1 m ode r egister 32 - t1 m ode t ransmit i nterface c ontrol r egister (ticr) h ex a ddress :0 x 0120 b it f unction t ype d efault d escription -o peration 7 txsyncfrd r/w 0 transmit synchronous fractional data interface 0 = fractional data is clocked into the chip using txchclk 1 = fractional data is clocked in to the chip using txserclk (ungapped). txchn[4:0] still indicates the time slot number if txfr1544 is not 1, tximode[1:0] = 00, and txmuxen = 0. txchclk is used as fractional da ta enable. 6 reserved - - reserved 5 txplclkenb r/w 0 transmit payload clock enable 1 = txserclk will output tx clock with oh bit perio d blocked in 1.544mhz clock output mode. txsync is low 0 txsync is low in h.100 and hmvip mode 0 = txsync is active low 1 = txsync is active high t able 45: t ransmit i nterface c ontrol r egister - e1 m ode r egister 32 - e1 m ode t ransmit i nterface c ontrol r egister (ticr) h ex a ddress :0 x 0120 b it f unction t ype d efault d escription -o peration
xrt86l30 65 single t1/e1/j1 framer/liu combo rev. 1.0.1 4 txfr1544 r/w 0 if txmuxen = 0 and tximode[1:0] = 00 0 = txchn[4:0] will output the channel number as us ual. 1 = txchn[0]/txsig will input signaling information and txchn[1]/txfrtd will input fractional channel data in 1.544 mbit mode. n ote : this bit has no effect while either txmuxen = 1 or tximode[1:0] = 00, txchn[4:0] signals input txsig and fractional d ata. 3 txiclkinv r/w 0 clock inversion 0 = data transition occurs on rising edge of the tr ansmit clock. 1 = data transition occurs on falling edge of the t ransmit clock. 2 txmuxen r/w 0 mux enable 0 = no channel multiplexing. 1 = four channels are multiplexed in single serial stream. 1 tximode[1] r/w 0 tx intf mode selection this mode selection determines the interface speed. when txmuxen = 0 00 = transmit interface is taking data at a rate of 1.544mbit/s. 01 = transmit interface is taking data at a rate of 2.048mbit/s. 10 = transmit interface is taking data at a rate of 4.096mbit/s. 11 = transmit interface is taking data at a rate of 8.192mbit/s. when txmuxen = 1, 00 = transmit interface is taking data at a rate of 12.352mbit/s from channel 0 and bit-demultiplexing into 4 channels from to the liu outputs on channels 0 through 3. the txsync pulse remains high during the framing bit of each ds-1 frame. 01 = transmit interface is taking data at a rate of 16.384mbit/s from channel 0 and bit-demultiplexing into 4 channels from to the liu outputs on channels 0 through 3. the txsync pulse remains high during the framing bit of each ds-1 frame. 10 = transmit interface is taking data at a rate of 16.384mbit/s from channel 0 and byte-demultiplexing into 4 channels from to the liu outputs on channels 0 through 3 (hmvip mode). the txsync pulse remains high during the last two bits of the previous ds-1 frame and the first t wo bits of the current ds-1 frame. 11 = transmit interface is taking data at a rate of 16.384mbit/s from channel 0 and byte-demultiplexing into 4 channels from to the liu outputs on channels 0 through 3 (h.100 mode). the txsync pulse remains high during the last bit of the previous ds-1 frame and the first bit of the current ds-1 frame. n ote : channel 4 is de-multiplexed into the liu outputs at channel 4 through 7. 0 tximode[0] r/w 0 t able 46: t ransmit i nterface c ontrol r egister - t1 m ode r egister 32 - t1 m ode t ransmit i nterface c ontrol r egister (ticr) h ex a ddress :0 x 0120 b it f unction t ype d efault d escription -o peration
xrt86l30 66 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 47: r eceive i nterface c ontrol r egister (ricr) - e1 m ode register 33 - e1 mode r eceive i nterface c ontrol r egister (ricr) 0 x 0122 b it f unction t ype d efault d escription -o peration 7 rxsyncfrd r/w 0 rx synchronous fractional data interf ace 0 = fractional data is clocked out from the chip us ing rxchclk 1 = rxchclk is used to output fractional data enabl e instead of being fraction data clock. in this mode, fractional data is clock ed out of the chip using rxserclk (ungapped). rxchn still indicates the time slot number if rxfr2048 is not 1, rximode[1:0] = 0, and rxmuxen = 0. 6 reserved - - reserved 5 rxplclkenb/ r/w 0 rx payload clock enable 1 = rxserclk outputs rx clock with oh bit period bl ocked while in 2.048mhz clock output mode. rxsyncislow rxsync is low in h.100 and hmvip mode 1 = rxsync active low. 0 = rxsync active high. 4 rxfr2048 r/w 0 clock inversion 1 = rxchn[0]/rxsig outputs signaling information, r xchn[1]/rxfrtd will out- put fractional channel data in 2.048 mhz mode and rxchn[2] will output the serial channel number of each time slot. 0 = rxchn[4:0] outputs the parallel channel number as usual. 3 rxiclkinv n/a 0 clock inversion 0 = data transition happens on the rising edge of t he transmit clocks. 1 = data transition happens on the falling edge of the transmit clocks. 2 rxmuxen r/w 0 mux enable 0 = no channel multiplexing. 1 = four channels are multiplexed in single serial stream.
xrt86l30 67 single t1/e1/j1 framer/liu combo rev. 1.0.1 1 rximode[1] r/w 0 rx intf mode selection this mode selection determines the interface speed. when rxmuxen = 0 00 = receive interface is presenting data at a rate of 2.048mbit/s. 01 = receive interface is presenting data at a rate of 2.048mbit/s. 10 = receive interface is presenting data at a rate of 4.096mbit/s. 11 = receive interface is presenting data at a rate of 8.192mbit/s. when rxmuxen = 1 00 = reserved 01 = receive interface is taking data from the four liu input channels 0 through 3 and byte-multiplexing into the serial out put channel 0. the txsync pulse remains high during the framing bit of each e1 frame. 10 = receive interface is taking data from the four liu input channels 0 through 3 and byte-multiplexing into the serial out put channel 0 (hmvip mode). the txsync pulse remains high during the last two bits of the pre- vious e1 frame and the first two bits of the curren t e1 frame. 11 = receive interface is taking data from the four liu input channels 0 through 3 and byte-multiplexing into the serial out put channel 0 (h.100 mode). the txsync pulse remains high during the last bit of the previous e1 frame and the first bit of the current e1 frame. n ote : channels 4 through 7 are multiplexed into the seria l output at channel 4. 0 rximode[0] r/w 0 t able 48: r eceive i nterface c ontrol r egister (ricr) - t1 m ode register 33 - t1 mode r eceive i nterface c ontrol r egister (ricr) 0 x 0122 b it f unction t ype d efault d escription -o peration 7 rxsyncfrd r/w 0 rx synchronous fractional data interf ace 1 = rxchclk is used to output fractional data inste ad of being fraction data clock. in this mode, fractional data is clocked out of the c hip using rxserclk (ungapped). rxchn still indicates the time slot number if rxfr1 544 is not 1, rximode[1:0] = 00, and rxmuxen = 0. rxcclk will be a valid signal for fractional data o utput (rxfrtd) if rxfr1544 is 1 or rximode[1:0] = 00 or rxmuxen = 0 6 reserved - - reserved 5 rxplclkenb/ r/w 0 rx payload clock enable 1 = rxserclk will output rx clock with oh bit perio d blocked while in 1.544mhz clock output mode. rxsyncislow rxsync is low in h.100 and hmvip mode 1 =rx sync active low. 0 = rxsync active high. t able 47: r eceive i nterface c ontrol r egister (ricr) - e1 m ode register 33 - e1 mode r eceive i nterface c ontrol r egister (ricr) 0 x 0122 b it f unction t ype d efault d escription -o peration
xrt86l30 68 rev. 1.0.1 single t1/e1/j1 framer/liu combo 4 rxfr1544 r/w 0 clock inversion/rxsig 1 = rxchn[0]/rxsig outputs signaling information, r xchn[1]/rxfrtd will out- put fractional channel data in 1.544 mhz mode and r xchn[2] will output the serial channel number of each time slot. 0 = rxchn[4:0] outputs the parallel channel number as usual. 3 rxiclkinv n/a 0 clock inversion 0 = data transition happens on the rising edge of t he transmit clocks. 1 = data transition happens on the falling edge of the transmit clocks. 2 rxmuxen r/w 0 mux enable 0 = no channel multiplexing. 1 = four channels are multiplexed in single serial stream. 1 rximode[1] r/w 0 rx interface mode selection this mode selection determines the interface speed. when rxmuxen = 0, 00 = receive interface is presenting data at a rate of 1.544mbit/s. 01 = receive interface is presenting data at a rate of 2.048mbit/s. 10 = receive interface is presenting data at a rate of 4.096mbit/s. 11 = receive interface is presenting data at a rate of 8.192mbit/s. when rxmuxen = 1, 00 = receive interface is taking data from the four liu input channels 0 through 3 and byte-multiplexing into a 12.352mhz se rial output on channel 0. the txsync pulse remains high during the framing bit of each ds-1 frame. 01 = receive interface is taking data from the four liu input channels 0 through 3 and byte-multiplexing into a 16.384mhz se rial output on channel 0. the txsync pulse remains high during the framing bit of each ds-1 frame. 10 = receive interface is taking data from the four liu input channels 0 through 3 and byte-multiplexing into a 16.384mhz se rial output on channel 0 (hmvip mode). the txsync pulse remains high duri ng the last two bits of the previous ds-1 frame and the first two bits of t he current ds-1 frame. 11 = receive interface is taking data from the four liu input channels 0 through 3 and byte-multiplexing into a 16.384mhz se rial output on channel 0 (h.100 mode). the txsync pulse remains high duri ng the last bit of the previous ds-1 frame and the first bit of the curren t ds-1 frame. n ote : channels 4 through 7 are multiplexed into the seria l output at channel 4. 0 rximode[0] r/w 0 t able 49: ds1 t est r egister register 34 ds1 test register (ds1tr) 0x0123 b it f unction t ype d efault d escription -o peration 7 prbstyp r/w 0 prbs pattern type 0 = the (x 15 + x 14 +1) pbrs polynomial is generated. 1 = qrts (quasi-random test signal) pattern is gene rated. 6 errorins r/w 0 error insertion 0 to 1 transition will cause one output bit inverte d t able 48: r eceive i nterface c ontrol r egister (ricr) - t1 m ode register 33 - t1 mode r eceive i nterface c ontrol r egister (ricr) 0 x 0122 b it f unction t ype d efault d escription -o peration
xrt86l30 69 single t1/e1/j1 framer/liu combo rev. 1.0.1 5 reserved - - reserved 4 rxprbslock r 0 lock status 0 = rx prbs has not locked. 1 = rx prbs has locked to the input patterns. 3 rxprbsenb r/w 0 rx prbs generation enable 0 = receive prbs checker is not enabled. 1 = receive prbs checker is enabled. 2 txprbsenb r/w 0 tx prbs generation enable 0 = tx prbs generator is not enabled. 1 = tx prbs generator is enabled. 1 rxds1bypass r/w 0 rx ds1 framer bypass 0 = disabled 1 = rx ds1 framer bypass mode. 0 txds1bypass r/w 0 tx ds1 framer bypass 0 = disabled 1 = tx ds1 framer bypass mode. t able 50: l oopback c ode c ontrol r egister register 35 l oopback c ode c ontrol r egister (lccr) 0 x 0124 b it f unction t ype d efault d escription -o peration 7-6 rxlbcdlen[1:0] r/w 0 receive loopback code activati on length determines the receive loopback code activation len gth. 00 = 4-bit sequence 01 = 5-bit sequence 10 = 6-bit sequence 11 = 7-bit sequence 5-4 rxlbcdlen[1:0] r/w 0 receive loopback code deactiva tion length determines the receive loopback code deactivation l ength 00 = 4-bit sequence 01 = 5-bit sequence 10 = 6-bit sequence 11 = 7-bit sequence 3-2 txlbcdlen[1:0] r/w 0 transmit loopback code length determines transmit loopback code length. 00 = 4-bit sequence 01 = 5-bit sequence 10 = 6-bit sequence 11 = 7-bit sequence t able 49: ds1 t est r egister register 34 ds1 test register (ds1tr) 0x0123 b it f unction t ype d efault d escription -o peration
xrt86l30 70 rev. 1.0.1 single t1/e1/j1 framer/liu combo 1 framed r 0 framed loopback code selects either framed or unframed loopback code ope ration. 0 = unframed 1 = framed 0 autoenb r/w 0 loopback automatically enables loopback automatically. 0 = automatic loopback is disabled 1 = automatic loopback is enabled t able 51: t ransmit l oopback c oder r egister register 36 tran smit loopback coder register (tlcr) 0x0125 b it f unction t ype d efault d escription -o peration 7-1 txlbc[6:0] r/w 1010101 transmit loopback code determines the transmit loopback coding sequence. 0 txlbcenb r/w 0 transmit loopback code enable enables loopback code generation. 0 = transmit loopback code is disabled. 1 = transmit loopback code is enabled t able 52: r eceive l oopback a ctivation c ode r egister register 37 receive loopba ck activation code register (rlacr) 0x0126 b it f unction t ype d efault d escription -o peration 7-1 rxlbac[6:0] r/w 1010101 receive activation loopback code determines the receive activation loopback coding s equence. 0 rxlbacenb r/w 0 receive activation loopback code enab le enables receive loopback code activation detection. 0 = receive loopback code activation detection is d isabled. 1 = receive loopback code activation detection is e nabled t able 53: r eceive l oopback d eactivation c ode r egister register 38 receive loopbac k deactivation code register (rldcr) 0x0127 b it f unction t ype d efault d escription -o peration 7-1 rxlbdc[6:0] r/w 1010101 receive deactivation loopba ck code determines the receive deactivation loopback coding sequence. 0 rxlbdcenb r/w 0 receive deactivation loopback code en able enables receive loopback code deactivation detectio n. 0 = receive loopback code deactivation detection is disabled. 1 = receive loopback code deactivation detection is enabled t able 50: l oopback c ode c ontrol r egister register 35 l oopback c ode c ontrol r egister (lccr) 0 x 0124 b it f unction t ype d efault d escription -o peration
xrt86l30 71 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 54: t ransmit sa s elect r egister register 39 t ransmit sa s elect r egister (tsasr) 0x0130 b it f unction t ype d efault d escription -o peration 7 txsa8sel r/w 0 sa8 bit determines whether sa8 is from serial input or regi ster. 0 = serial input. 1 = sa8 register. 6 txsa7sel r/w 0 sa7 bit select determines whether sa7 is from serial input or regi ster. 0 = serial input. 1 = sa7 register 5 txsa6sel r/w 0 sa6 bit select determines whether sa6 is from serial input or regi ster. 0 = serial input. 1 = sa6 register 4 txsa5sel r/w 0 sa5 bit select determines whether sa5 is from serial input or regi ster. 0 = serial input. 1 = sa5 register 3 txsa4sel r/w 0 sa4 bit select determines whether sa4 is from serial input or regi ster. 0 = serial input. 1 = sa4 register 2 lb1enb r/w 0 loopback 1 auto enable local loopback is activated while the followings ha ppened from the transmit serial input. sa5 = 0 and sa6 = 1111 occur for 8 consecutive time s. a = 1 1 lb2enb r/w 0 loopback 2 auto enable local loopback is activated while the followings ha ppened from the transmit serial input. sa5 = 0 and sa6 = 1010 occur for 8 consecutive time s. a = 1 0 lbrenb r/w 0 loopback release enable local loopback is released while the followings hap pened from the transmit serial input. sa5 = 0 and sa6 = 0000 occur for 8 consecutive time s. t able 55: t ransmit sa a uto c ontrol r egister 1 register 40 t ransmit sa a uto c ontrol r egister 1 (tsacr1) 0x0131 b it f unction t ype d efault d escription -o peration 7 loslfa_1_enb r/w 0 los/lfa 1 auto transmit 6 los_1_enb r/w 0 los 1 auto transmit
xrt86l30 72 rev. 1.0.1 single t1/e1/j1 framer/liu combo the following table demonstrates the conditions on the receive side which trigger the actions while th ese bits are enabled. 5 loslfa_2_enb r/w 0 los/lfa 2 auto transmit 4 loslfa_3_enb r/w 0 los/lfa 3 auto transmit 3 loslfa_4_enb r/w 0 los/lfa 4 auto transmit 2 nop_enb r/w 0 no power auto transmit 1 nop_loslfa_enb r/w 0 no power and los/lfa auto transm it 0 los_2_enb r/w 0 los 3 auto transmit t able 56: c onditions on r eceive side w hen tsacr1 bits a re enabled c onditions a ctions - sending pattern c omments a s a 5 s a 6 loslfa_1_enb: loss of signal or loss of frame alignment x 1 0000 los/lfa at te (fc2) los_1_enb: loss of signal 1 1 1110 los (fc3) loslfa_2_enb: los or lfa 1 0 0000 los/lfa (fcl) loslfa_3_enb: los or lfa 0 1 1100 los/lfa (fc4) loslfa_4_enb: los or lfa 0 1 1110 los/lfa (fc3&fc4) nop_enb: loss of power 0 1 1000 loss of power at nt1 nop_loslfa_enb: loss of power and los or lfa 1 1 1000 loss of power and los/lfa los_2_enb: los auxp pattern los (fc1). transmit auxp pattern t able 57: t ransmit sa a uto c ontrol r egister 2 register 41 t ransmit sa a uto c ontrol r egister (tsacr2) 0x013 2 b it f unction t ype d efault d escription -o peration 7 ais_1_enb r/w 0 ais reception 6 ais_2_enb r/w 0 ais reception t able 55: t ransmit sa a uto c ontrol r egister 1 register 40 t ransmit sa a uto c ontrol r egister 1 (tsacr1) 0x0131 b it f unction t ype d efault d escription -o peration
xrt86l30 73 single t1/e1/j1 framer/liu combo rev. 1.0.1 the following table demonstrates the conditions on receive side which trigger the actions while these bit are enabled. 5 reserved - - reserved 4 reserved - - reserved 3-2 crcrep_enb r/w 0 crc report 1 crcdet_enb r/w 0 crc detection 0 crcrec/det_enb r/w 0 crc report and detect t able 58: c onditions on r eceive side w hen tsacr1 bits enabled c onditions a ctions - sending pattern for a s a 5 s a 6 e ais_1_enb 1 1 1111 x ais_2_enb 0 1 1111 x crcrep_enb = 01, crc reported (e = 0) 0 1 0000 0 crcrep_enb = 10, crc reported 0 0 0000 0 crcrep_enb = 11, crc reported 0 1 0001 1 crcdet_enb 0 1 0010 1 crcdet/rep_enb 0 1 0011 1 t able 59: t ransmit sa4 r egister register 42 t ransmit sa4 r egister (tsa4r) 0x0133 b it f unction t ype d efault d escription -o peration 7-0 txsa4[7:0] r/w 11111111 sa4 the content of this register sources the transmit s a4 bits while txsa4enb (register 0x010ah) is 1 and txsa4sel (regi ster 0x0130h) is 1. bit 7 is transmitted in frame 2 of the crc-4 multif rame, bit 6 is in frame 4, etc. t able 57: t ransmit sa a uto c ontrol r egister 2 register 41 t ransmit sa a uto c ontrol r egister (tsacr2) 0x013 2 b it f unction t ype d efault d escription -o peration
xrt86l30 74 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 60: t ransmit sa5 r egister register 43 t ransmit sa5 r egister (tsa5r) 0x0134 b it f unction t ype d efault d escription -o peration 7-0 txsa5[7:0] r/w 11111111 sa5 the content of this register sources the transmit s a5 bits while txsa5enb (register 0x010ah) is 1 and txsa5sel (regi ster 0x0130h) is 1. bit 7 is transmitted in frame 2 of the crc-4 multif rame, bit 6 is in frame 4, etc. t able 61: t ransmit sa6 r egister register 44 t ransmit sa6 r egister (tsa6r) 0x0135 b it f unction t ype d efault d escription -o peration 7-0 txsa6[7:0] r/w 11111111 sa6 the content of this register sources the transmit s a6 bits while txsa6enb (register 0x010ah) is 1 and txsa6sel (regi ster 0x0130h) is 1. bit 7 is transmitted in frame 2 of the crc-4 multif rame, bit 6 is in frame 4, etc. t able 62: t ransmit sa7 r egister register 45 t ransmit sa7 r egister (tsa7r) 0x0136 b it f unction t ype d efault d escription -o peration 7-0 txsa7[7:0] r/w 11111111 sa7 the content of this register sources the transmit s a7 bits while txsa7enb (register 0x010ah) is 1 and txsa7sel (regi ster 0x0130h) is 1. bit 7 is transmitted in frame 2 of the crc-4 multif rame, bit 6 is in frame 4, etc. t able 63: t ransmit sa8 r egister register 46 t ransmit sa8 r egister (tsa8r) 0x0137 b it f unction t ype d efault d escription -o peration 7-0 txsa8[7:0] r/w 11111111 sa8 the content of this register sources the transmit s a8 bits while txsa8enb (register 0x010ah) is 1 and txsa8sel (regi ster 0x0130h) is 1. bit 7 is transmitted in frame 2 of the crc-4 multif rame, bit 6 is in frame 4, etc.
xrt86l30 75 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 64: r eceive s a 4 r egister register 47 r eceive s a 4 r egister (rsa4r) 0x013b b it f unction t ype d efault d escription -o peration 7-0 rxsa4[7:0] ro 11111111 sa4 the content of this register stores the received sa 4 bits if rxsa4enb (register 0x010ch) is 1. bit 7 is received in frame 2 of the crc-4 multifram e, bit 6 is in frame 4, etc. t able 65: r eceive s a 5 r egister register 48 r eceive s a 5 r egister (rsa5r) 0x013c b it f unction t ype d efault d escription -o peration 7-0 rxsa5[7:0] ro 11111111 sa5 the content of this register stores the received sa 5 bits if rxsa5enb (register 0x010ch) is 1. bit 7 is received in frame 2 of the crc-4 multifram e, bit 6 is in frame 4, etc. t able 66: r eceive s a 6 r egister r egister 49 r eceive s a 6 r egister (rsa6r) 0 x 013d b it f unction t ype d efault d escription -o peration 7-0 rxsa6[7:0] ro 11111111 sa6 the content of this register stores the received sa 6 bits if rxsa6enb (register 0x010ch) is 1. bit 7 is received in frame 2 of the crc-4 multifram e, bit 6 is in frame 4, etc. t able 67: r eceive s a 7 r egister r egister 50 r eceive s a 7 r egister (rsa7r) 0 x 013e b it f unction t ype d efault d escription -o peration 7-0 rxsa7[7:0] ro 11111111 sa7 the content of this register stores the received sa 7 bits if rxsa7enb (register 0x010ch) is 1. bit 7 is received in frame 2 of the crc-4 multifram e, bit 6 is in frame 4, etc.
xrt86l30 76 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 68: r eceive s a 8 r egister r egister 51 r eceive s a 8 r egister (rsa8r) 0 x 013f b it f unction t ype d efault d escription -o peration 7-0 rxsa8[7:0] ro 11111111 sa8 the content of this register stores the received sa 8 bits if rxsa8enb (register 0x010ch) is 1. bit 7 is received in frame 2 of the crc-4 multifram e, bit 6 is in frame 4, etc. t able 69: d ata l ink c ontrol r egister r egister 52 d ata l ink c ontrol r egister 2 (dlcr2) h ex a ddress : 0 x 0143 b it f unction t ype d efault d escription -o peration 7 slc-96 r/w 0 slc ? 96 enable, 6 bit for esf if slc ? 96 framing is selected, setting this bit high will enable slc ? 96 data link transmission; otherwise, the regular s f framing bits are transmitted. in esf framing mode, setting this bit high will cau se facility data link to transmit/receive slc ? 96-like message. 6 mosa r/w 0 mos abort enable/disable select this read/write bit-field is used to configure the transmit hdlc2 controller to automatically transmit an abort seque nce anytime it transitions from the mos mode to the bos mode. 0 = transmit hdlc2 controller inserts an mos abort sequence if the mos message is interrupted 1 = prevents transmit hdlc2 controller from inserti ng an mos abort sequence. 5 rx_fcs_dis r/w 0 receive fcs verification disable enables/disables receive hdlc2 controllers computa tion and verification of the fcs value in the incoming lapd message frame 0 = verifies fcs value of each mos frame. 1 = does not verify fcs value of each mos frame. 4 autorx r/w 0 auto receive lapd message configures the rx hdlc2 controller to discard any i ncoming lapd message frame that exactly match which is currently stored in the rx hdlc2 buffer. 0 = disabled 1 = enables this feature. 3 tx_abort r/w 0 transmit abort configures the tx hdlc2 controller to transmit an a bort sequence (string of 7 or more consecutive 1s) to t he remote termi- nal. 0 = tx hdlc2 controller operates normally 1 = tx hdlc2 controller inserts an abort sequence i nto the data link channel.
xrt86l30 77 single t1/e1/j1 framer/liu combo rev. 1.0.1 2 tx_idle r/w 0 transmit idle (flag sequence byte) configures the tx hdlc2 controller to transmit a st ring of flag sequence octets (0x7e) in the data link channel to the remote ter- minal. 0 = tx hdlc2 controller resumes transmitting data t o the remote terminal 1 = tx hdlc2 controller transmits a string of flag sequence bytes. n ote : this bit-field is ignored if the tx hdlc2 controlle r is operating in the bos mode - bit-field 0(mos/bos) wi thin this register is set to 0. 1 tx_fcs_en r/w 0 transmit lapd message with fcs configure hdlc2 controller to include/not include f cs octets in the outbound lapd message frames. 0 = does not include fcs octets into the outbound l apd message frame. 1 = inserts fcs octets into the outbound lapd messa ge frame. n ote : this bit-field is ignored if the transmit hdlc2 con troller has been configured to operate in the bos mode. 0 mos/bos r/w 0 message oriented signaling/bit oriented signali ng select specifies whether the txrx hdlc2 controller will be transmitting and receiving lapd message frames (mos) or bit orie nted signal (bos) messages. 0 = tx/rx hdlc2 controller transmits and receives b os messages. 1 = tx/rx hdlc2 controller transmits and receives m os mes- sages. t able 70: t ransmit d ata l ink b yte c ount r egister r egister 53 t ransmit d ata l ink b yte c ount r egister 2 (tdlbcr2) h ex a ddress : 0 x 0144 b it f unction t ype d efault d escription -o peration 7 bufaval//bufsel r/w 0 transmit hdlc2 buffer available /buffer select specifies which of the two tx hdlc2 buffers that th e tx hdlc2 controller should read from to generate the next ou tbound hdlc2 message. 0 = transmits message data residing in tx hdlc2 buf fer 0. 1 = transmits message data residing in tx hdlc2 buf fer 1. n ote : if one of these tx hdlc2 buffers contain a message which has yet to be completely read-in and processed for transmission by the tx hdlc2 controller, then this bit-field will automatically reflect the value corresponding to the available buffer. changing this bit-field to the in -use buffer is not permitted. t able 69: d ata l ink c ontrol r egister r egister 52 d ata l ink c ontrol r egister 2 (dlcr2) h ex a ddress : 0 x 0143 b it f unction t ype d efault d escription -o peration
xrt86l30 78 rev. 1.0.1 single t1/e1/j1 framer/liu combo 6 tdlbc6 r/w 0 transmit hdlc2 message - byte count depends on whether an mos or bos message is being t ransmitted to the remote terminal equipment if bos message is being transmitted : these bit fields contain the number of repetitions the bos message must be trans mitted before the tx hdlc2 controller generates the txeot interru pt and halts transmission. if these fields are set to 00000000, then the bos mes- sage will be transmitted for an indefinite number o f times. if mos message is being transmitted: these bit fields contain the length, in number of octets, of the message to be t ransmitted. 5 tdlbc5 r/w 0 4 tdlbc4 r/w 0 3 tdlbc3 r/w 0 2 tdlbc2 r/w 0 1 tdlbc1 r/w 0 0 tdlbc0 r/w 0 t able 71: r eceive d ata l ink b yte c ount r egister r egister 54 r eceive d ata l ink b yte c ount r egister 2 (rdlbcr2) h ex a ddress : 0 x 0145 b it f unction t ype d efault d escription -o peration 7 rbufptr r/w 0 receive hdlc2 buffer-pointer identifies which rxhdlc2 buffer contains the newly received hdlc2 message. 0 = hdlc2 message is stored in rx hdlc2 buffer 0. 1 = hdlc2 message is stored in rx hdlc2 buffer 1. 6 rdlbc6 r/w 0 re ceive hdlc message - byte count in mos mode these seven bit-fields contain the size in bytes of the hdlc2 mes- sage that has been extracted and written into the r x hdlc2 buffer. in bos mode these bits should be set to the value of the messag e repetitions before each receive interrupt. if they are set to 0, no rxeot inter- rupt will be generated. 5 rdlbc5 r/w 0 4 rdlbc4 r/w 0 3 rdlbc3 r/w 0 2 rdlbc2 r/w 0 1 rdlbc1 r/w 0 0 rdlbc0 r/w 0 t able 70: t ransmit d ata l ink b yte c ount r egister r egister 53 t ransmit d ata l ink b yte c ount r egister 2 (tdlbcr2) h ex a ddress : 0 x 0144 b it f unction t ype d efault d escription -o peration
xrt86l30 79 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 72: d ata l ink c ontrol r egister r egister 55 d ata l ink c ontrol r egister 3 (dlcr3) h ex a ddress : 0 x 0153 b it f unction t ype d efault d escription -o peration 7 slc-96 r/w 0 slc ? 96 enable, 6 bit for esf if slc ? 96 framing is selected, setting this bit high will enable slc ? 96 data link transmission; otherwise, the regular s f framing bits are transmitted. in esf framing mode, setting this bit high will cau se facility data link to transmit/receive slc ? 96-like message. 6 mosa r/w 0 mos abort enable/disable select this read/write bit-field is used to configure the transmit hdlc3 controller to automatically transmit an abort seque nce anytime it transitions from the mos mode to the bos mode. 0 = transmit hdlc3 controller inserts an mos abort sequence if the mos message is interrupted 1 = prevents transmit hdlc3 controller from inserti ng an mos abort sequence. 5 rx_fcs_dis r/w 0 receive fcs verification disable enables/disables receive hdlc3 controllers computa tion and verification of the fcs value in the incoming lapd message frame 0 = verifies fcs value of each mos frame. 1 = does not verify fcs value of each mos frame. 4 autorx r/w 0 auto receive lapd message configures the rx hdlc3 controller to discard any i ncoming lapd message frame that exactly match which is currently stored in the rx hdlc3 buffer. 0 = disabled 1 = enables this feature. 3 tx_abort r/w 0 transmit abort configures the tx hdlc3 controller to transmit an a bort sequence (string of 7 or more consecutive 1s) to t he remote termi- nal. 0 = tx hdlc3 controller operates normally 1 = tx hdlc3 controller inserts an abort sequence i nto the data link channel. 2 tx_idle r/w 0 transmit idle (flag sequence byte) configures the tx hdlc3 controller to transmit a st ring of flag sequence octets (0x7e) in the data link channel to the remote ter- minal. 0 = tx hdlc3 controller resumes transmitting data t o the remote terminal 1 = tx hdlc3 controller transmits a string of flag sequence bytes. n ote : this bit-field is ignored if the tx hdlc3 controlle r is operating in the bos mode - bit-field 0(mos/bos) wi thin this register is set to 0.
xrt86l30 80 rev. 1.0.1 single t1/e1/j1 framer/liu combo 1 tx_fcs_en r/w 0 transmit lapd message with fcs configure hdlc3 controller to include/not include f cs octets in the outbound lapd message frames. 0 = does not include fcs octets into the outbound l apd message frame. 1 = inserts fcs octets into the outbound lapd messa ge frame. n ote : this bit-field is ignored if the transmit hdlc3 con troller has been configured to operate in the bos mode. 0 mos/bos r/w 0 message oriented signaling/bit oriented signali ng select specifies whether the txrx hdlc3 controller will be transmitting and receiving lapd message frames (mos) or bit orie nted signal (bos) messages. 0 = tx/rx hdlc3 controller transmits and receives b os messages. 1 = tx/rx hdlc3 controller transmits and receives m os mes- sages. t able 73: t ransmit d ata l ink b yte c ount r egister r egister 56 t ransmit d ata l ink b yte c ount r egister 3 (tdlbcr3) h ex a ddress : 0 x 0154 b it f unction t ype d efault d escription -o peration 7 bufaval//bufsel r/w 0 transmit hdlc3 buffer available /buffer select specifies which of the two tx hdlc3 buffers that th e tx hdlc3 controller should read from to generate the next ou tbound hdlc3 message. 0 = transmits message data residing in tx hdlc3 buf fer 0. 1 = transmits message data residing in tx hdlc3 buf fer 1. n ote : if one of these tx hdlc3 buffers contain a message which has yet to be completely read-in and processed for transmission by the tx hdlc3 controller, then this bit-field will automatically reflect the value corresponding to the available buffer. changing this bit-field to the in -use buffer is not permitted. 6 tdlbc6 r/w 0 transmit hdlc3 message - byte count depends on whether an mos or bos message is being t ransmitted to the remote terminal equipment if bos message is being transmitted : these bit fields contain the number of repetitions the bos message must be trans mitted before the tx hdlc3 controller generates the txeot interru pt and halts transmission. if these fields are set to 00000000, then the bos mes- sage will be transmitted for an indefinite number o f times. if mos message is being transmitted: these bit fields contain the length, in number of octets, of the message to be t ransmitted. 5 tdlbc5 r/w 0 4 tdlbc4 r/w 0 3 tdlbc3 r/w 0 2 tdlbc2 r/w 0 1 tdlbc1 r/w 0 0 tdlbc0 r/w 0 t able 72: d ata l ink c ontrol r egister r egister 55 d ata l ink c ontrol r egister 3 (dlcr3) h ex a ddress : 0 x 0153 b it f unction t ype d efault d escription -o peration
xrt86l30 81 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 74: r eceive d ata l ink b yte c ount r egister r egister 57 r eceive d ata l ink b yte c ount r egister 3 (rdlbcr3) h ex a ddress : 0 x 0155 b it f unction t ype d efault d escription -o peration 7 rbufptr r/w 0 receive hdlc3 buffer-pointer identifies which rxhdlc3 buffer contains the newly received hdlc3 message. 0 = hdlc3 message is stored in rx hdlc3 buffer 0. 1 = hdlc3 message is stored in rx hdlc3 buffer 1. 6 rdlbc6 r/w 0 re ceive hdlc message - byte count in mos mode these seven bit-fields contain the size in bytes of the hdlc3 mes- sage that has been extracted and written into the r x hdlc3 buffer. in bos mode these bits should be set to the value of the messag e repetitions before each receive interrupt. if they are set to 0, no rxeot inter- rupt will be generated. 5 rdlbc5 r/w 0 4 rdlbc4 r/w 0 3 rdlbc3 r/w 0 2 rdlbc2 r/w 0 1 rdlbc1 r/w 0 0 rdlbc0 r/w 0 t able 75: d evice id r egister r egister 58 d evice id r egister (devid) 0 x 01fe b it f unction t ype d efault d escription -o peration 7-0 devid[7:0] ro 00110111 devid this register is used to identify the xrt86l30 fram er/liu. the value of this register is 0x37h. t able 76: r evision id r egister r egister 59 r evision id r egister (revid) 0 x 01ff b it f unction t ype d efault d escription -o peration 7-0 revid[7:0] ro 00000001 revid this register is used to identify the revision numb er of the xrt86l30. the value of this register for revision a is 0x01h. t able 77: t ransmit c hannel c ontrol r egister 0 to 31 e1 m ode r egister 60-91 e1 t ransmit c hannel c ontrol r egister 0-31 (tccr 0-31) h ex a ddress : 0 x 0300 to 0 x 031f b it m od e f unction t ype d efault d escription -o peration 7-6 e1 lapdcntl r/w 10 lapd control these bits select which lapd controller is to be ac tivated. 00 = lapd1 01 = lapd2 10 = txde[1:0] will determine the data source for t he d/e time slots 11 = lapd3
xrt86l30 82 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 78: t ransmit c hannel c ontrol r egister 0 to 31 t1 m ode r egister 60-91 t1 t ransmit c hannel c ontrol r egister 0-23 (tccr 0-23) h ex a ddress : 0 x 0300 to 0 x 0317 b it f unction t ype d efault d escription -o peration 7-6 lapdcntl r/w 10 lapd control these bits select which lapd controller is to be ac tivated. 00 = lapd1 01 = lapd2 10 = txde[1:0] will determine the data source for t he d/e time slots 11 = lapd3 t able 79: t ransmit u ser c ode r egister 0 to 31 r egister 92-123 t1/e1 t ransmit u ser c ode r egister 0 (ucr 0-31) h ex a ddress : 0 x 0320 to 0 x 033f b it f unction t ype d efault d escription -o peration 7-0 tucr[7:0] r/w 0 programmable user code. t able 80: t ransmit s ignaling c ontrol r egister x - e1 m ode r egister 124-155 - e1 t ransmit s ignaling c ontrol r egister x (tscr 0-31) h ex a ddress : 0 x 0340 to 0 x 035f b it f unction t ype d efault d escription -o peration 7 a (x) r/w 0 (1) signaling bit a or x bit a,b,c,d: these are programmable signaling informati on. note: time slot 16 of frame 0 is controlled by tscr 0 (for 0 bits) and tscr16 (for xyxx bits). 6 b (y) r/w 0 (0) signaling bit b or y bit 5 c (x) r/w 0 (1) signaling bit c or x bit 4 d (x) r/w 0 (1) signaling bit d or x bit 3 reserved - - reserved 2 reserved - - reserved 1 txsigsrc[1] r/w 0 channel signaling control these bits determine the selection of signaling con ditioning. 00 = no signaling data is inserted into input pcm d ata (passthrough). 01 = signaling data is inserted from tscrs. 10 = signaling data is inserted from txoh input whi le txmuxen=0 and tximode[1:0]=00, otherwise is inserted from txsig input. 11 = no signaling. for xyxx bits only, x's are from tscr and y is the alarm condition. 0 txsigsrc[0] r/w 0
xrt86l30 83 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 81: t ransmit s ignaling c ontrol r egister x - t1 m ode r egister 124-155 - t1 t ransmit s ignaling c ontrol r egister x (tscr) (0-23) h ex a ddress : 0 x 0340 to 0 x 035f b it f unction t ype d efault d escription -o peration 7 a (x) r/w 0 (1) signaling bit a a,b,c,d: these are programmable signaling informati on. 6 b (y) r/w 0 (0) signaling bit b 5 c (x) r/w 0 (1) signaling bit c 4 d (x) r/w 0 (1) signaling bit d 3 reserved - - reserved 2 rob_enb r/w 0 robbed-bit signaling enable this bit enables robbed-bit signaling transmission. 0 = robbed-bit is disabled. 1 = robbed-bit is enabled 1 txsigsrc[1] r/w 0 channel signaling control these bits determine the selection of signaling con ditioning. 00 = no signaling data is inserted into input pcm d ata. 01 = signaling data is inserted from tscrs. 10 = signaling data is inserted from txsig input. 11 = no signaling. 0 txsigsrc[0] r/w 0 t able 82: r eceive c hannel c ontrol r egister x (rccr 0-31) - e1 m ode r egister 156-187 e1 r eceive c hannel c ontrol r egister x (rccr 0-31) h ex a ddress : 0 x 0360 to 0 x 037f b it f unction t ype d efault d escription -o peration 7-6 lapdcntl r/w 10 lapd control these bits select which lapd controller is to be ac tivated. 00 = lapd1 01 = lapd2 10 = rxde[1:0] will determine the data source for t he d/e time slots 11 = lapd3 5-4 reserved - - reserved
xrt86l30 84 rev. 1.0.1 single t1/e1/j1 framer/liu combo 3 rxcond[3] r/w 0 selects data conditioning these bits determines the type of data condition ap plying to input pcm data. 0x0 = the input pcm data is unchanged. 0x1 = all 8 bits of the pcm channel data are invert ed. 0x2 = the even bits of input data are inverted. 0x3 = the odd bits of input data are inverted. 0x4 = data in user code register shown in table 3-2 7 replaces the input data. 0x5 = busy ff code (0xff)) replaces the input data. 0x6 = busy 0vcode (0xd5) replaces the input data. 0x7 = busy ts (111#_####) replaces the input data; ##### is timeslot number. 0x8 = busy 00 (0x00) replaces the input data. 0x9 = the a-law digital milliwatt pattern replaces the input data. 0xa = the m-law digital milliwatt pattern replaces the input data. 0xb = the msb (bit 1) of input data is inverted. 0xc = all input data except msb is inverted. 0xd = prbs, qrts/x 15 + x 14 +1. 0xe = the input pcm data bit are unchanged. 0xf = this is a d/e time slots. see receive signali ng data link select register 12. (rs&dlsr) 2 rxcond[2] r/w 0 1 rxcond[1] r/w 0 0 rxcond[0] r/w 0 t able 83: r eceive c hannel c ontrol r egister x (rccr 0-23) - t1 m ode r egister 156-187 - t1 r eceive c hannel c ontrol r egister x (rccr 0-23) h ex a ddress : 0 x 0360 to 0 x 037f b it f unction t ype d efault d escription -o peration 7-6 lapdcntl r/w 10 lapd control these bits select which lapd controller is to be ac tivated. 00 = lapd1 01 = lapd2 10 = rxde[1:0] will determine the data source for t he d/e time slots 11 = lapd3 5 rxzero[1] r/w 0 selects type of zero suppression these bits select the zero code suppression used. 00 = no zero code suppression is used. 01 = at&t bit 7 stuffing is used. 10 = gte zero code suppression is used. bit 8 is st uffed in non-sig- naling frame. otherwise, bit 7 is stuffed in signal ing frame if the signal- ing bit is zero. 11 = dds zero code suppression is applied. 4 rxzero[0] r/w 0 t able 82: r eceive c hannel c ontrol r egister x (rccr 0-31) - e1 m ode r egister 156-187 e1 r eceive c hannel c ontrol r egister x (rccr 0-31) h ex a ddress : 0 x 0360 to 0 x 037f b it f unction t ype d efault d escription -o peration
xrt86l30 85 single t1/e1/j1 framer/liu combo rev. 1.0.1 3 rxcond[3] r/w 0 selects data conditioning these bits determines the type of data condition ap plying to input pcm data. 0x0 = the input pcm data is unchanged. 0x1 = all 8 bits of the pcm channel data are invert ed. 0x2 = the even bits of input data are inverted. 0x3 = the odd bits of input data are inverted. 0x4 = data in user (idle) code register (table 3?49 ) replaces the input data for transmission. 0x5 = busy code (0x7f)) replaces the input data for transmission. 0x6 = vacant code (0xff) replaces the input data fo r transmis- sion. 0x7 = busy ts (111#_####) replaces the input data f or transmis- sion; ##### is timeslot number. 0x8 = moof (0x1a) replaces the input data for trans mission. 0x9 = the a-law digital milliwatt pattern replaces the input data. 0xa = the m-law digital milliwatt pattern replaces the input data. 0xb = the msb (bit 1) of input data is inverted. 0xc = all input data except msb is inverted. 0xd = prbs, qrts/x 15 + x 14 + 1. 0xe = the input pcm data bit are unchanged. 0xf = this is a d/e time slots. see receive signali ng data link select register 12. (rs&dlsr) 2 rxcond[2] r/w 0 1 rxcond[1] r/w 0 0 rxcond[0] r/w 0 t able 84: r eceive u ser c ode r egister x (rucr 0-31) r egister 188-219 t1/e1 r eceive u ser c ode r egister x (rucr 0-31) h ex a ddress : 0 x 0380 to 0 x 039f b it f unction t ype d efault d escription -o peration 7 rxuser[7] r/w 1 programmable user code 6 rxuser[6] r/w 1 5 rxuser[5] r/w 1 4 rxuser[4] r/w 1 3 rxuser[3] r/w 1 2 rxuser[2] r/w 1 1 rxuser[1] r/w 1 0 rxuser[0] r/w 1 t able 83: r eceive c hannel c ontrol r egister x (rccr 0-23) - t1 m ode r egister 156-187 - t1 r eceive c hannel c ontrol r egister x (rccr 0-23) h ex a ddress : 0 x 0360 to 0 x 037f b it f unction t ype d efault d escription -o peration
xrt86l30 86 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 85: r eceive s ignaling c ontrol r egister x (rscr) (0-31) r egister 220-251 t1/e1 r eceive s ignaling c ontrol r egister x (rscr) (0-31) h ex a ddress : 0 x 03a0 to 0 x 03bf b it f unction t ype d efault d escription -o peration 6 sigc_enb r/w 0 signaling substitution enable this bit enables signaling substitution. 0 = substitution is disabled. 1 = substitution is enabled. 5 oh_enb r/w 0 signaling oh interface output enable this bit enables outputting signaling through overh ead interface. the information in receive signaling array register s is output to receive overhead interface. 0 = output is disabled. 1 = output is enabled. 4 deb_enb r/w 0 per-channel debounce enable this bit enables signaling debounce feature. 0 = debounce is disabled. 1 = debounce is enabled. 3 rxsigc[1] r/w 0 signaling conditioning these bits control per-channel signaling substituti on. 00 = substitutes all signaling bits with one. 01 = enables 16-code (sig16-a,b,c,d) signaling subs titution. 10 = enables 4-code (sig4-a,b) signaling substituti on. 11 = enables 2-code (sig2-a) signaling substitution . 2 rxsigc[0] r/w 0 1 rxsige[1] r/w 0 signaling extraction. these bits determines the extracted signaling codin g. 00 = no signaling is extracted. 01 = extracts 16-code signaling. 10 = extracts 4-code signaling. 11 = extracts 2-code signaling. 0 rxsige[0] r/w 0 t able 86: r eceive s ubstitution s ignaling r egister (rssr) e1 m ode r egister 252-283 e1 m ode r eceive s ubstitution s ignaling r egister (rssr 0-31) h ex a ddress 0 x 03c0 to 0 x 03df b it f unction t ype d efault d escription -o peration 6 sig2-a r/w 0 2-code signaling a 5 sig4-b r/w 0 4-code signaling b 4 sig4-a r/w 0 4-code signaling a 3 sig16-d r/w 0 16-code signaling d 2 sig16-c r/w 0 16-code signaling c 1 sig16-b r/w 0 16-code signaling b 0 sig16-a r/w 0 16-code signaling a
xrt86l30 87 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 87: r eceive s ubstitution s ignaling r egister (rssr) t1 m ode r egister 252-283 - t1 r eceive s ubstitution s ignaling r egister (rssr 0-23) h ex a ddress : 0 x 03c0 to 0 x 03df b it f unction t ype d efault d escription -o peration 7-4 reserved - - reserved 3 sig16-a, 4-a, 2-a r/w 0 16-code signaling a 4-code si gnaling a 2-code signaling a 2 sig16-b, 4-b, 2-a r/w 0 16-code signaling b 4-code si gnaling b 2-code signaling a 1 sig16-c, 4-a, 2-a r/w 0 16-code signaling c 4-code si gnaling a 2-code signaling a 0 sig16-d, 4-b, 2-a r/w 0 16-code signaling d 4-code si gnaling b 2-code signaling a t able 88: r eceive s ignaling a rray r egister 0 to 31 r egister 284-315 r eceive s ignaling a rray r egister (rsar 0-31) h ex a ddress : 0 x 0500 to 0 x 051f b it f unction t ype d efault d escription -o peration 7-4 reserved - - reserved 3 a r/w 0 reflects the most recently received signaling value (a,b,c,d) asso- ciated with timeslot 0 to 31. n ote : the content of this register only has meaning when the framer is using channel associated signaling. 2 b r/w 0 1 c r/w 0 0 d r/w 0 t able 89: lapd b uffer 0 c ontrol r egister r egister 316-411 lapd b uffer 0 c ontrol r egister (lapdbcr0) h ex a ddress : 0 x 0600 to 0 x 0660 b it f unction t ype d efault d escription -o peration 7-0 lapd buffer 0 r/w 0 lapd buffer 0 (96-bytes) this register is used to transmit and receive lapd messages within buffer 0 of the hdlc controller chosen in the lapd select register (0x011b). when writing to buffer 0, the message is inserted into the outgoing lapd frame and the data cannot be retrieve d. after detecting the rx end of transfer interrupt (rxeot), the extracted lapd message is available to be read. n ote : when writing or reading from buffer 0, the register is automatically incremented such that 0x0600 can be w ritten to or read from continuously.
xrt86l30 88 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 90: lapd b uffer 1 c ontrol r egister r egister 412-507 lapd b uffer 0 c ontrol r egister (lapdbcr1) h ex a ddress : 0 x 0700 to 0 x 0760 b it f unction t ype d efault d escription -o peration 7-0 lapd buffer 1 r/w 0 lapd buffer 1 (96-bytes) this register is used to transmit and receive lapd messages within buffer 1 of the hdlc controller chosen in the lapd select register (0x011b). when writing to buffer 1, the message is inserted into the outgoing lapd frame and the data cannot be retrieve d. after detecting the rx end of transfer interrupt, the ext racted lapd mes- sage is available to be read. n ote : when writing or reading from buffer 1, the register is automatically incremented such that 0x0700 can be w ritten to or read from continuously. t able 91: pmon t1/e1 r eceive l ine c ode ( bipolar ) v iolation c ounter r egister 508 pmon r eceive l ine c ode ( bipolar ) v iolation c ounter msb (rlcvcu) h ex a ddress : 0 x 0900 b it f unction t ype d efault d escription -o peration 7 rlcvc[15] rur 0 these eight bits represent the msb fo r the 16-bit line code viola- tion counter. 6 rlcvc[14] rur 0 5 rlcvc[13] rur 0 4 rlcvc[12] rur 0 3 rlcvc[11] rur 0 2 rlcvc[10] rur 0 1 rlcvc[9] rur 0 0 rlcvc[8] rur 0 t able 92: pmon t1/e1 r eceive l ine c ode ( bipolar ) v iolation c ounter r egister 509 pmon r eceive l ine c ode ( bipolar ) v iolation c ounter lsb (rlcvcl) h ex a ddress : 0 x 0901 b it f unction t ype d efault d escription -o peration 7 rlcvc[7] rur 0 these eight bits represent the lsb for the 16-bit line code violation counter. 6 rlcvc[6] rur 0 5 rlcvc[5] rur 0 4 rlcvc[4] rur 0 3 rlcvc[3] rur 0 2 rlcvc[2] rur 0 1 rlcvc[1] rur 0 0 rlcvc[0] rur 0
xrt86l30 89 single t1/e1/j1 framer/liu combo rev. 1.0.1 .. t able 93: pmon t1/e1 r eceive f raming a lignment b it e rror c ounter r egister 510 pmon r eceive f raming a lignment e rror c ounter msb (rfaecu) h ex a ddress : 0 x 0902 b it f unction t ype d efault d escription -o peration 7 rfaec[15] rur 0 these eight bits represent the msb fo r the 16-bit receive framing alignment error counter. 6 rfaec[14] rur 0 5 rfaec[13] rur 0 4 rfaec[12] rur 0 3 rfaec[11] rur 0 2 rfaec[10] rur 0 1 rfaec[9] rur 0 0 rfaec[8] rur 0 t able 94: pmon t1/e1 r eceive f raming a lignment b it e rror c ounter r egister 511 pmon r eceive f raming a lignment e rror c ounter lsb (rfaecl) h ex a ddress : 0 x 0903 b it f unction t ype d efault d escription -o peration 7 rfaec[7] rur 0 these eight bits represent the lsb for the 16-bit receive framing alignment error counter. 6 rfaec[6] rur 0 5 rfaec[5] rur 0 4 rfaec[4] rur 0 3 rfaec[3] rur 0 2 rfaec[2] rur 0 1 rfaec[1] rur 0 0 rfaec[0] rur 0 t able 95: pmon t1/e1 r eceive s everely e rrored f rame c ounter r egister 512 pmon r eceive s everely e rrored f rame c ounter (rsefc) h ex a ddress : 0 x 0904 b it f unction t ype d efault d escription -o peration 7 rsefc[7] rur 0 severely errored 8-bit frame accumulat ion counter note: a severely errored frame event is defined as the occurrence of two consecutive errored frame alignment signals tha t are not responsible for loss of frame alignment. 6 rsefc[6] rur 0 5 rsefc[5] rur 0 4 rsefc[4] rur 0 3 rsefc[3] rur 0 2 rsefc[2] rur 0 1 rsefc[1] rur 0 0 rsefc[0] rur 0
xrt86l30 90 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 96: pmon t1/e1 r eceive crc-4 b lock e rror c ounter - msb r egister 513 pmon r eceive s ynchronization b it b lock e rror c ounter (rsbbecu) h ex a ddress : 0 x 0905 b it f unction t ype d efault d escription -o peration 7 rsbbec[15] rur 0 these eight bits represent the msb f or the 16-bit receive synchro- nization bit block error counter. 6 rsbbec[14] rur 0 5 rsbbec[13] rur 0 4 rsbbec[12] rur 0 3 rsbbec[11] rur 0 2 rsbbec[10] rur 0 1 rsbbec[9] rur 0 0 rsbbec[8] rur 0 t able 97: pmon t1/e1 r eceive crc-4 b lock e rror c ounter - lsb r egister 514 pmon r eceive s ynchronization b it b lock e rror c ounter (rsbbecl) h ex a ddress : 0 x 0906 b it f unction t ype d efault d escription -o peration 7 rsbbec[7] rur 0 these eight bits represent the lsb fo r the 16-bit receive synchroni- zation bit block error counter. 6 rsbbec[6] rur 0 5 rsbbec[5] rur 0 4 rsbbec[4] rur 0 3 rsbbec[3] rur 0 2 rsbbec[2] rur 0 1 rsbbec[1] rur 0 0 rsbbec[0] rur 0
xrt86l30 91 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 98: pmon t1/e1 r eceive f ar -e nd bl ock e rror c ounter - msb r egister 515 pmon r eceive f ar -e nd b lock e rror c ounter (rfebecu) h ex a ddress : 0 x 0907 b it f unction t ype d efault d escription -o peration 7 rfebec[15] rur 0 these eight bits represent the msb f or the 16-bit receive far-end block error counter. 6 rfebec[14] rur 0 5 rfebec[13] rur 0 4 rfebec[12] rur 0 3 rfebec[11] rur 0 2 rfebec[10] rur 0 1 rfebec[9] rur 0 0 rfebec[8] rur 0 t able 99: pmon t1/e1 r eceive f ar e nd b lock e rror c ounter r egister 516 pmon r eceive f ar e nd b lock e rror c ounter (rfebecl) h ex a ddress : 0 x 0908 b it f unction t ype d efault d escription -o peration 7 rfebec[7] rur 0 these eight bits represent the lsb fo r the 16-bit receive far-end block error counter. note: counter contains the 16-bit far-end block err or event. counter will increment once each time the received e-bit is set to zero. the counter is disabled during loss of sync at either t he fas or crc-4 level and it will continue to count if loss of mult iframe sync occurs at the cas level. 6 rfebec[6] rur 0 5 rfebec[5] rur 0 4 rfebec[4] rur 0 3 rfebec[3] rur 0 2 rfebec[2] rur 0 1 rfebec[1] rur 0 0 rfebec[0] rur 0 t able 100: pmon t1/e1 r eceive s lip c ounter r egister 517 pmo n r eceive s lip c ounter (rsc) h ex a ddress : 0 x 0909 b it f unction t ype d efault d escription -o peration 7 rsc[7] rur 0 note: counter contains the 8-bit receive buffer slip event. a slip event is defined as a replication or deletion of a t1/e1 frame by the receiving slip buffer. note: a 16 bit counter which counts the occurrence of a bipolar vio- lation on the receive data line. this counter is of sufficient length so that the probability of counter saturation over a o ne second interval at a 10 -3-bit error rate (ber) is less than 0.001% . 6 rsc[6] rur 0 5 rsc[5] rur 0 4 rsc[4] rur 0 3 rsc[3] rur 0 2 rsc[2] rur 0 1 rsc[1] rur 0 0 rsc[0] rur 0
xrt86l30 92 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 101: pmon t1/e1 r eceive l oss of f rame c ounter r egister 518 pmon r eceive l oss of f rame c ounter (rlfc) h ex a ddress : 0 x 090a b it f unction t ype d efault d escription -o peration 7 rlfc[7] rur 0 note: lofc (8-bit counter) is a count o f the number of times a "loss of fas frame" has been declared. this counter provi des the capa- bility to measure an accumulation of short failure events. 6 rlfc[6] rur 0 5 rlfc[5] rur 0 4 rlfc[4] rur 0 3 rlfc[3] rur 0 2 rlfc[2] rur 0 1 rlfc[1] rur 0 0 rlfc[0] rur 0 t able 102: pmon t1/e1 r eceive c hange of f rame a lignment c ounter r egister 519 pmon r eceive c hange of f rame a lignment c ounter (rcfac) h ex a ddress : 0 x 090b b it f unction t ype d efault d escription -o peration 7 rcfac[7] rur 0 change of frame alignment accumulation counter. note: (8-bit counter) cofa is declared when the new ly-locked fram- ing is different from the one offered by off-line f ramer. 6 rcfac[6] rur 0 5 rcfac[5] rur 0 4 rcfac[4] rur 0 3 rcfac[3] rur 0 2 rcfac[2] rur 0 1 rcfac[1] rur 0 0 rcfac[0] rur 0 t able 103: pmon lapd t1/e1 f rame c heck s equence e rror c ounter 1 r egister 520 pmon lapd1 f rame c heck s equence e rror c ounter 1 (lfcsec1) h ex a ddress : 0 x 090c b it f unction t ype d efault d escription -o peration 7 fcsec1[7] rur 0 frame check sequence error accumulati on counter 1. note: 8-bit counter accumulates the times of occurr ence of receive frame check sequence error detected by lapd1 contro ller. 6 fcsec1[6] rur 0 5 fcsec1[5] rur 0 4 fcsec1[4] rur 0 3 fcsec1[3] rur 0 2 fcsec1[2] rur 0 1 fcsec1[1] rur 0 0 fcsec1[0] rur 0
xrt86l30 93 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 104: t1/e1 prbs b it e rror c ounter msb r egister 521 t1/e1 prbs b it e rror c ounter msb (pbecu) h ex a ddress : 0 x 090d b it f unction t ype d efault d escription -o peration 7 prbse[15] rur 0 most significant bits of prbs bit err or accumulation 16-bit counter 6 prbse[14] rur 0 5 prbse[13] rur 0 4 prbse[12] rur 0 3 prbse[11] rur 0 2 prbse[10] rur 0 1 prbse[9] rur 0 0 prbse[8] rur 0 t able 105: t1/e1 prbs b it e rror c ounter lsb r egister 522 t1/e1 prbs b it e rror c ounter lsb (pbecl) h ex a ddress : 0 x 090e b it f unction t ype d efault d escription -o peration 7 prbse[7] rur 0 least significant byte of prbs bit err or accumulation 16-bit counter. 6 prbse[6] rur 0 5 prbse[5] rur 0 4 prbse[4] rur 0 3 prbse[3] rur 0 2 prbse[2] rur 0 1 prbse[1] rur 0 0 prbse[0] rur 0 t able 106: t1/e1 t ransmit s lip c ounter r egister 523 t1/e1 t ransmit s lip c ounter (t1/e1tsc) h ex a ddress : 0 x 090f b it f unction t ype d efault d escription -o peration 7 txslip[7] rur 0 transmit slip accumulation counter. 6 txslip[6] rur 0 5 txslip[5] rur 0 4 txslip[4] rur 0 3 txslip[3] rur 0 2 txslip[2] rur 0 1 txslip[1] rur 0 0 txslip[0] rur 0
xrt86l30 94 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 107: t1/e1 e xcessive z ero v iolation c ounter msb r egister 524 t1/e1 e xcessive z ero v iolation c ounter msb (ezvcu) h ex a ddress : 0 x 0910 b it f unction t ype d efault d escription -o peration 7 ezvc[15] rur 0 these eight bits represent the msb for the 16-bit excessive zero violation counter. 6 ezvc[14] rur 0 5 ezvc[13] rur 0 4 ezvc[12] rur 0 3 ezvc[11] rur 0 2 ezvc[10] rur 0 1 ezvc[9] rur 0 0 ezvc[8] rur 0 t able 108: t1/e1 e xcessive z ero v iolation c ounter lsb r egister 525 t1/e1 e xcessive z ero v iolation c ounter msb (ezvcl) h ex a ddress : 0 x 0911 b it f unction t ype d efault d escription -o peration 7 ezvc[7] rur 0 these eight bits represent the lsb for the 16-bit excessive zero violation counter. 6 ezvc[6] rur 0 5 ezvc[5] rur 0 4 ezvc[4] rur 0 3 ezvc[3] rur 0 2 ezvc[2] rur 0 1 ezvc[1] rur 0 0 ezvc[0] rur 0 t able 109: t1/e1 f rame c heck s equence e rror c ounter 2 r egister 526 pmon lapd2 f rame c heck s equence e rror c ounter 2 (lfcsec2) h ex a ddress : 0 x 091c b it f unction t ype d efault d escription -o peration 7 fcsec2[7] rur 0 frame check sequence error accumulati on counter 2. note: 8-bit counter accumulates the times of occurr ence of receive frame check sequence error detected by lapd2 contro ller. 6 fcsec2[6] rur 0 5 fcsec2[5] rur 0 4 fcsec2[4] rur 0 3 fcsec2[3] rur 0 2 fcsec2[2] rur 0 1 fcsec2[1] rur 0 0 fcsec2[0] rur 0
xrt86l30 95 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 110: t1/e1 f rame c heck s equence e rror c ounter 3 r egister 527 pmon lapd3 f rame c heck s equence e rror c ounter 3 (lfcsec3) h ex a ddress : 0 x 092c b it f unction t ype d efault d escription -o peration 7 fcsec3[7] rur 0 frame check sequence error accumulati on counter 3. note: 8-bit counter accumulates the times of occurr ence of receive frame check sequence error detected by lapd3 contro ller. 6 fcsec3[6] rur 0 5 fcsec3[5] rur 0 4 fcsec3[4] rur 0 3 fcsec3[3] rur 0 2 fcsec3[2] rur 0 1 fcsec3[1] rur 0 0 fcsec3[0] rur 0 t able 111: b lock i nterrupt s tatus r egister r egister 528 b lock i nterrupt s tatus r egister (bisr) h ex a ddress : 0 x 0b00 b it f unction t ype d efault d escription -o peration 7 sa6 ro 0 sa6 interrupt status 6 lbcode ro 0 loopback code interrupt 5 rxclklos rur 0 rxclk los interrupt status indicates if framer n has experienced a loss of rec overed clock interrupt since last read of this register. 0 = loss of recovered clock interrupt has not occur red since last read of this register 1 = loss of recovered clock interrupt has occurred since last read of this register. 4 onesec rur 0 one second interrupt status indicates if the xrt86l30 has experienced a one sec ond interrupt since the last read of this register. 0 = no outstanding one second interrupts awaiting s ervice 1 = outstanding one second interrupt awaits service 3 hdlc ro 0 hdlc block interrupt status indicates if the hdlc block has an interrupt reques t awaiting ser- vice. 0 = no outstanding interrupt requests awaiting serv ice 1 = hdlc block has an interrupt request awaiting se rvice. interrupt service routine should branch to and read data link status register (address xa,06). n ote : this bit-field will be reset to 0 after the micropr ocessor has performed a read to the data link status register.
xrt86l30 96 rev. 1.0.1 single t1/e1/j1 framer/liu combo 2 slip ro 0 slip buffer block interrupt status indicates if the slip buffer block has any outstand ing interrupt requests awaiting service. 0 = no outstanding interrupts awaiting service 1 = slip buffer block has an interrupt awaiting ser vice. interrupt ser- vice routine should branch to and read slip buffer interrupt status register (address 0xxa,0x09. n ote : this bit-field will be reset to 0 after the micropr ocessor has performed a read of the slip buffer interrupt statu s register. 1 alarm ro 0 alarm & error block interrupt status indicates if the alarm & error block has any outsta nding interrupts that are awaiting service. 0 = no outstanding interrupts awaiting service 1 = alarm & error block has an interrupt awaiting s ervice. interrupt serstatus register (address xa,02) n ote : this bit-field will be reset to 0 after the micropr ocessor has performed a read of the alarm & error interrupt sta tus register. 0 t1/e1 frame ro 0 t1/e1 framer block interrupt status indicates if an t1/e1 frame status interrupt reques t is awaiting ser- vice. 0 = no t1/e1 frame status interrupt is pending 1 = t1/e1 framer status interrupt is awaiting servi ce. t able 112: b lock i nterrupt e nable r egister r egister 529 b lock i nterrupt e nable r egister (bier) h ex a ddress : 0 x 0b01 b it f unction t ype d efault d escription -o peration 7 sa6_enb r/w 0 sa6 interrupt enable 6 lbcode_enb r/w 0 loopback code interrupt enable 5 rxclkloss r/w 0 rxlineclk loss interrupt enable 0 = disables interrupt 1 = enables interrupt 4 onesec_enb r/w 0 one second interrupt enable 0 = disables interrupt 1 = enables interrupt 3 hdlc_enb r/w 0 hdlc block interrupt enable 0 = disables all hdlc block interrupts 1 = enables hdlc block (for interrupt generation) a t the block level 2 slip_enb r/w 0 slip buffer block interrupt enable 0 = disables all slip buffer block interrupts 1 = enables slip buffer block at the block level t able 111: b lock i nterrupt s tatus r egister r egister 528 b lock i nterrupt s tatus r egister (bisr) h ex a ddress : 0 x 0b00 b it f unction t ype d efault d escription -o peration
xrt86l30 97 single t1/e1/j1 framer/liu combo rev. 1.0.1 1 alarm_enb r/w 0 alarm & error block interrupt enable 0 = disables all alarm & error block interrupts 1 = enables alarm & error block at the block level 0 t1/e1frame_enb r/w 0 t1/e1 frame block enable 0 = disables all frame block interrupts 1 = enables the frame block at the block level t able 113: a larm & e rror i nterrupt s tatus r egister r egister 530 a larm & e rror i nterrupt s tatus r egister (aeisr) h ex a ddress : 0 x 0b02 b it m od e f unction t ype d efault d escription -o peration 7 e1/ t1 rxlof state ro 0 receive loss of frame state reflects a current loss of framing condition as det ected by the receive t1/e1 framer. 0 = receive framer not declaring loss of framing co ndition 1 = receive framer declaring loss of framing condit ion 6 e1/ t1 rxais state ro 0 receive alarm indication status state this read only bit field indicates whether or not t he receive t1/e1 frame is currently detecting an ais pattern in the incoming data stream. 0 = receive framer not detecting ais pattern in inc oming t1/e1 data stream 1 = receive framer detecting ais pattern in incomin g t1/e1 data stream 5 e1 rxmyel status rur 0 receipt of cas multiframe yello w alarm interrupt status. the receive e1 framer will set this bit-field to 1 if i t detects the cas multiframe yellow alarm in the incoming e1 data str eam. 0 = receipt of cas multiframe yellow alarm interrup t has not occurred since the last read of this register. 1 = receipt of cas multiframe yellow alarm interrup t has occurred since the last read of this register. 5 t1 rxyel_state r 0 yellow alarm state indicates a yellow alarm has been received. 0 = no yellow alarm is received 1 = yellow alarm is received 4 e1/ t1 los status rur 0 loss of signal interrupt status. the receive e1 framer will set this bit-field to 1 if it detects a consecutive str ing of 0s at the rxpox_n and rx0eg_n input pins for 32 bit period. 0 = los interrupt has not occurred since the last r ead of this regis- ter 1 = los interrupt has occurred since the last read of this register t able 112: b lock i nterrupt e nable r egister r egister 529 b lock i nterrupt e nable r egister (bier) h ex a ddress : 0 x 0b01 b it f unction t ype d efault d escription -o peration
xrt86l30 98 rev. 1.0.1 single t1/e1/j1 framer/liu combo 3 e1/ t1 lcv int status rur 0 line code violation interrupt status . the receive liu interrupt block will set this bit-field to 1 if it detects a line code violation in the incoming e1 data stream. 0 = line code violation interrupt has not occurred since the last read of this register. 1 = line code violation interrupt has occurred sinc e the last read of this register. 2 e1/ t1 rxlof status rur 0 change in receive loss of frame condition interrupt st atus . the receive e1 framer block will set this bit-field to 1 if the receive e1 framer has transition into the in-frame conditio n or loss of frame condition. 0 = change in rxlof interrupt has not occurred sinc e the last read of this register 1 = change in rxlof interrupt has occurred since th e last read of this register 1 e1/ t1 rxais status rur 0 change in receive ais condition interrupt status . the receive e1 framer will generate the change in ais condition interrupt if it starts to detect the ais pattern in the incoming da ta stream or if it no longer detects the ais pattern in the incoming data stream. 0 = change in ais condition interrupt has not occur red since the last read of this register 1 = change in ais condition interrupt has occurred since the last read of this register 0 e1/ t1 rxyel status rur 0 receipt of fas frame yellow alarm i nterrupt status. the receive e1 framer will generate the fas frame y ellow alarm interrupt if it detects the fas frame yellow alarm in the incoming e1 data stream. 0 = fas frame yellow alarm interrupt has not occurr ed 1 = fas frame yellow alarm interrupt has occurred s ince the last read of this register. t able 114: a larm & e rror i nterrupt e nable r egister - e1 m ode r egister 531 e1 m ode a larm & e rror i nterrupt e nable r egister (aeier) h ex a ddress : 0 x 0b03 b it f unction t ype d efault d escription -o peration 7-6 reserved - - reserved 5 rxmyel enb r/w 0 multiframe yellow alarm state change interrupt enable enables the generation of an interrupt when the yel low alarm has been received. 0 = a multiframe yellow alarm (y bit equals to 1) w ill not generate an interrupt. 1 = a multiframe yellow alarm will generate an inte rrupt. t able 113: a larm & e rror i nterrupt s tatus r egister r egister 530 a larm & e rror i nterrupt s tatus r egister (aeisr) h ex a ddress : 0 x 0b02 b it m od e f unction t ype d efault d escription -o peration
xrt86l30 99 single t1/e1/j1 framer/liu combo rev. 1.0.1 4 los enb r/w 0 loss of signal interrupt enable enables the interrupt generation when the loss of s ignal has been detected. 0 = disables the interrupt generation of los detect ion. 1 = enables the interrupt generation of los detecti on 3 bpv enb r/w 0 bipolar violation interrupt enable enables the interrupt generation of a bipolar viola tion. 0 = disables the interrupt generation of a bipolar violation condition. 1 = enables the interrupt generation of a bipolar v iolation condition. 2 rxlof enb r/w 0 red alarm state change interrupt enab le enables the interrupt generation when the change st ate of red alarm has been detected. 0 = disables the interrupt generation of loss of fr ame detection. 1 = enables the interrupt generation of loss of fra me detection. 1 rxais enb r/w 0 ais state change interrupt enable enables the generation of an interrupt when the cha nge state of ais event has been detected. 0 = the state change of ais does not generate an in terrupt. 1 = the state change of ais does generate an interr upt. 0 rxyel enb r/w 0 yellow alarm state change interrupt e nable enables the generation of an interrupt when the yel low alarm has been received. 0 = a yellow alarm (a bit equals to 1) will not gen erate an interrupt. 1 = a yellow alarm will generate an interrupt t able 115: a larm & e rror i nterrupt e nable r egister -t1 m ode r egister 531 t1 m ode a larm & e rror i nterrupt e nable r egister (aeier) h ex a ddress : 0 x 0b03 b it f unction t ype d efault d escription -o peration 7-5 reserved - - reserved 4 los enb r/w 0 loss of signal interrupt enable enables the interrupt generation when the loss of s ignal has been detected. 0 = disables the interrupt generation of los detect ion. 1 = enables the interrupt generation of los detecti on. 3 bpv enb r/w 0 bipolar violation interrupt enable enables the interrupt generation of a bipolar viola tion. 0 = disables the interrupt generation of a bipolar violation condition. 1 = enables the interrupt generation of a bipolar v iolation condition. t able 114: a larm & e rror i nterrupt e nable r egister - e1 m ode r egister 531 e1 m ode a larm & e rror i nterrupt e nable r egister (aeier) h ex a ddress : 0 x 0b03 b it f unction t ype d efault d escription -o peration
xrt86l30 100 rev. 1.0.1 single t1/e1/j1 framer/liu combo 1 2 rxred enb r/w 0 red alarm state change interrupt enab le enables the interrupt generation when the change st ate of red alarm has been detected. 0 = disables the interrupt generation of framing mi mic detection. 1 = enables the interrupt generation of framing mim ic detection. 1 rxais enb r/w 0 ais state change interrupt enable enable the generation of an interrupt when the chan ge state of ais event has been detected. 0 = the state change of ais does not generate an in terrupt. 1 = the state change of ais does generate an interr upt 0 rxyel enb r/w 0 yellow alarm state change interrupt e nable enables the generation of an interrupt when the cha nge state of yel- low alarm has been detected. 0 = any state change of yellow alarm will not gener ate an interrupt. 1 = changing state of yellow alarm will generate an interrupt. t able 116: f ramer i nterrupt s tatus r egister e1 m ode r egister 532 e1 m ode f ramer i nterrupt s tatus r egister (fisr) h ex a ddress : 0 x 0b04 b it f unction t ype d efault d escription -o peration 7 comfa status e1 only rur 0 change in cas multiframe alignment interrupt st atus 0 = change in cas multiframe alignment interrupt ha s not occurred since the last read of this register 1 = change in cas multiframe alignment interrupt ha s occurred since the last read of this register 6 nbit status e1 only rur 0 change in national bits interrupt status the receive e1 framer will generate this interrupt if it has detected a change in the national bits in the incoming non-f as e1 frames. 0 = change in national bits interrupt has not occur red since the last read of this register 1 = change in national bits interrupt has occurred since the last read of this register. 5 sig status rur 0 change in cas signaling interrupt st atus the receive e1 framer will generate this interrupt if it detects a change in the four-bit signaling values for any one of the 30 voice channels. 0 = change in cas signaling interrupt has not occur red since the last read of this register 1 = change in cas signaling interrupt has occurred since the last read of this register. 4 cofa status rur 0 change of fas frame alignment inter rupt status 0 = change in fas frame alignment interrupt has not occurred since the last read of this register 1 = change in fas frame alignment interrupt has occ urred since the last read of this register t able 115: a larm & e rror i nterrupt e nable r egister -t1 m ode r egister 531 t1 m ode a larm & e rror i nterrupt e nable r egister (aeier) h ex a ddress : 0 x 0b03 b it f unction t ype d efault d escription -o peration
xrt86l30 101 single t1/e1/j1 framer/liu combo rev. 1.0.1 1 3 if status rur 0 change of in frame condition interrup t status 2 fmd status rur 0 1 sync error status rur 0 crc-4 error interrupt status. the receive e1framer will declare this interrupt if it detects an error in the crc-4 bits within a given sub-multiframe. 0 = sync error has not occurred since the last read of this register 1 = sync error has occurred since the last read of this register 0 framing error status rur 0 0 = framing bit error inte rrupt has not occurred since the last read of this register 1 = framing bit error interrupt has occurred since the last read of this register t able 117: f ramer i nterrupt s tatus r egister t1 m ode r egister 532 t1 m ode f ramer i nterrupt s tatus r egister (fisr) h ex a ddress : 0 x 0b04 b it f unction t ype d efault d escription -o peration 5 sig rur/ wc 0 signaling updated this bit indicates the occurrence of state change o f any signaling channel. 0 = no state change occurs of any signaling. 1 = change of signaling state occurs. 4 cofa rur/ wc 0 change of frame alignment this bit is used to indicate that the receive synch ronization signal has changed alignment with respect to its last mult iframe position. 0 = no cofa occurs. 1 = cofa occurs. 3 if rur/ wc 0 in-frame state this bit indicates the occurrence of state change o f in-frame indica- tion. 0 = no state change occurs of in-frame indication. 1 = in-frame indication has changed state. 2 fmd rur/ wc 0 frame mimic state change this bit indicates the occurrence of state change o f framing mimic detection. 0 = no state change occurs of framing mimic detecti on. 1 = framing mimic detection has changed state. t able 116: f ramer i nterrupt s tatus r egister e1 m ode r egister 532 e1 m ode f ramer i nterrupt s tatus r egister (fisr) h ex a ddress : 0 x 0b04 b it f unction t ype d efault d escription -o peration
xrt86l30 102 rev. 1.0.1 single t1/e1/j1 framer/liu combo 1 se rur/ wc 0 synchronization bit error this bit indicates the occurrence of synchronizatio n bit error event. 0 = no synchronization bit error occurs. 1 = synchronization bit error occurs. 0 fe rur/ wc 0 framing error this bit is used to indicate that one or more frame alignment bit error have occurred. this bit doesn't not necessarily ind icate that syn- chronization has been lost. 0 = no framing bit error occurs. 1 = framing bit error occurs. t able 118: f ramer i nterrupt e nable r egister e1 m ode r egister 533 e1 m ode f ramer i nterrupt e nable r egister (fier) h ex a ddress : 0 x 0b05 b it f unction t ype d efault d escription -o peration 7 comfa enb - e1 only r/w 0 change in cas multiframe al ignment interrupt enable - e1 only 0 = disables the change in cas multiframe alignment interrupt 1 = enables the change in cas multiframe alignment interrupt 6 nbit enb - e1 only r/w 0 change in national bits inte rrupt enable - e1 only 0 = disables the change in national bits interrupt 1 = enables the change in national bits interrupt 5 sig enb r/w 0 change in cas signaling bits interrupt enable 0 = disables the change in cas signaling bits inter rupt enable 1 = enables the change in cas signaling bits interr upt enable 4 cofa enb r/w 0 change in fas framing alignment interr upt enable 0 = disables the change in fas framing alignment in terrupt enable 1 = enables the change in fas framing alignment int errupt enable 3 if enb r/w 0 if enable 2 fmd enb r/w 0 fmd enable 1 se_enb r/w 0 sync (crc-4) error interrupt enable 0 = sync error interrupt disabled 1 = sync error interrupt enabled 0 fe_enb r/w0 0 framing bit error interrupt enable 0 = disables the framing bit error interrupt 1 = enables the framing bit error interrupt t able 117: f ramer i nterrupt s tatus r egister t1 m ode r egister 532 t1 m ode f ramer i nterrupt s tatus r egister (fisr) h ex a ddress : 0 x 0b04 b it f unction t ype d efault d escription -o peration
xrt86l30 103 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 119: f ramer i nterrupt e nable r egister t1 m ode r egister 533 t1 m ode f ramer i nterrupt e nable r egister (fier) h ex a ddress : 0 x 0b05 b it f unction t ype d efault d escription -o peration 5 sig_enb r/w 0 this bits enables the generation of an interrupt when any signaling channel has changed state. 0 = change of signaling data does not generate an i nterrupt. 1 = change of signaling data does generate an inter rupt. 4 cofa_enb r/w 0 setting this bit will enable the inter rupt generation when the frame search logic determines that frame alignment has be en reached and that the new alignment differs from the previous al ignment. 0 = disables the interrupt generation of cofa detec tion. 1 = enables the interrupt generation of cofa detect ion. 3 if_enb r/w 0 if enable setting this bit will enable the interrupt generati on of an in-frame rec- ognition. 0 = disables the interrupt generation of an in-fram e detection. 1 = enables the interrupt generation of an in-frame detection. 2 fmd_enb r/w 0 fmd enable setting this bit will enable the interrupt generati on when the frame search logic detects the presence of framing bit mi mics. 0 = disables the interrupt generation of framing mi mic detection. 1 = enables the interrupt generation of framing mim ic detection. 1 se_enb r/w 0 sync (crc-4) error interrupt enable setting this bit will enable the generation of an i nterrupt when a syn- chronization bit error event has been detected. a synchronization bit error event is defined as crc-4 error. 0 = the detection of synchronization bit errors doe s not generate an interrupt. 1 = the detection of synchronization bit errors doe s generate an interrupt 0 fe_enb r/w0 0 framing bit error interrupt enable this bits enables the generation of an interrupt wh en a framing bit error has been detected. 0 = any error in the framing bits does not generate an interrupt. 1 = a error in the framing bits does generate an in terrupt.
xrt86l30 104 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 120: d ata l ink s tatus r egister 1 r egister 534 d ata l ink s tatus r egister 1 (dlsr1) h ex a ddress : 0 x 0b06 b it f unction t ype d efault d escription -o peration 7 msg type rur 0 hdlc1 message type identifier indicates type of data link message received by rx hdlc1 control- ler 0 = bit oriented signaling type data link message r eceived 1 = message oriented signaling type data link messa ge received 6 txsot rur 0 transmit hdlc1 start of transmission inte rrupt status indicates if the transmit hdlc1 start of transmissi on interrupt has occurred since the last read of this register. tran smit hdlc1 con- troller will declare this interrupt when it has sta rted to transmit a data link message. 0 = transmit hdlc1 start of transmission interrupt has not occurred since the last read of this register 1 = transmit hdlc1 start of transmission interrupt has occurred since the last read of this register. 5 rxsot rur 0 receive hdlc1 start of reception interrup t status indicates if the receive hdlc1 start of reception i nterrupt has occurred since the last read of this register. rece ive hdlc1 con- troller will declare this interrupt when it has sta rted to receive a data link message. 0 = receive hdlc1 start of reception interrupt has not occurred since the last read of this register 1 = receive hdlc1 start of reception interrupt has occurred since the last read of this register 4 txeot rur 0 transmit hdlc1 end of transmission interr upt status indicates if the transmit hdlc1 end of transmission interrupt has occurred since the last read of this register. tran smit hdlc1 con- troller will declare this interrupt when it has com pleted its transmis- sion of a data link message. 0 = transmit hdlc1 end of transmission interrupt ha s not occurred since the last read of this register 1 = transmit hdlc1 end of transmission interrupt ha s occurred since the last read of this register 3 rxeot rur 0 receive hdlc1 controller end of reception interrupt status indicates if receive hdlc1 end of reception interru pt has occurred since the last read of this register. receive hdlc1 controller will declare this interrupt once it has completely recei ved a full data link message. 0 = receive hdlc1 end of reception interrupt has no t occurred since the last read of this register 1 = receive hdlc1 end of reception interrupt has oc curred since the last read of this register
xrt86l30 105 single t1/e1/j1 framer/liu combo rev. 1.0.1 2 fcs error rur 0 fcs error interrupt status indicates if the fcs error interrupt has occurred s ince the last read of this register. receive hdlc1 controller will dec lare this interrupt if it detects an error in the most recently receive d data message. 0 = fcs error interrupt has not occurred since last read of this regis- ter 1 = fcs error interrupt has occurred since last rea d of this register 1 rx abort rur 0 receipt of abort sequence interrupt st atus indicates if the receipt of abort interrupt has occ urred since last read of this register. receive hdlc1 controller wil l declare this interrupt if it detects a string of seven (7) conse cutive 1s in the incoming data link channel. 0 = receipt of abort sequence interrupt has not occ urred since last read of this register 1 = receipt of abort sequence interrupt has occurre d since last read of this register 0 rxidle rur 0 receipt of idle sequence interrupt statu s indicates if the receipt of idle sequence interrupt has occurred since the last read of this register. the receive h dlc1 controller will declare this interrupt if it detects the flag sequence octet (0x7e) in the incoming data link channel. 0 = receipt of idle sequence interrupt has not occu rred since last read of this register 1 = receipt of idle sequence interrupt has occurred since last read of this register. t able 121: d ata l ink i nterrupt e nable r egister 1 r egister 535 d ata l ink i nterrupt e nable r egister 1 (dlier1) h ex a ddress : 0 x 0b07 b it f unction t ype d efault d escription -o peration 7 reserved - - reserved 6 txsot enb r/w 0 transmit hdlc1 start of transmission interrupt enable 0 = disables the transmit hdlc1 start of transmissi on interrupt 1 = enables the transmit hdlc1 start of transmissio n interrupt 5 rxsot enb r/w 0 receive hdlc1 start of reception inte rrupt enable 0 = disables the receive hdlc1 start of reception i nterrupt 1 = enables the receive hdlc1 start of reception in terrupt 4 txeot enb r/w 0 transmit hdlc1 end of transmission in terrupt enable 0 = disables the transmit hdlc1 end of transmission interrupt 1 = enables the transmit hdlc1 end of transmission interrupt 3 rxeot enb r/w 0 receive hdlc1 end of reception interr upt enable 0 = disables the receive hdlc1 end of reception int errupt 1 = enables the receive hdlc1 end of reception inte rrupt t able 120: d ata l ink s tatus r egister 1 r egister 534 d ata l ink s tatus r egister 1 (dlsr1) h ex a ddress : 0 x 0b06 b it f unction t ype d efault d escription -o peration
xrt86l30 106 rev. 1.0.1 single t1/e1/j1 framer/liu combo 2 fcs err enb r/w 0 fcs error interrupt enable 0 = disables fcs error interrupt 1 = enables fcs error interrupt 1 rxabort enb r/w 0 receipt of abort sequence interrupt enable 0 = disables receipt of abort sequence interrupt 1 = enables receive of abort sequence interrupt 0 rxidle enb r/w 0 receipt of idle sequence interrupt e nable 0 = disables receipt of idle sequence interrupt 1 = enables receipt of idle sequence interrupt t able 122: s lip b uffer i nterrupt s tatus r egister (sbisr) r egister 536 s lip b uffer i nterrupt s tatus r egister (sbisr) h ex a ddress : 0 x 0b08 b it f unction t ype d efault d escription -o peration 7 txsb_full rur/ wc 0 slip buffer fills & a frame is deleted this bit is set when the elastic store fills and a frame is deleted. 6 txsb_empt rur/ wc 0 slip buffer empties and a frame is repeated this bit is set when the elastic store empties and a frame is repeated. 5 txsb_slip rur/ wc 0 receive slips this bit is set when the slip buffer slips. 4 96lock r 0 slc ? 96 is in sync this bit indicates that slc96 is in sync. 3 mlock r 0 multiframe is in sync this bit indicates that multiframe is in sync. 2 sb_full rur/ wc 0 slip buffer fills & a frame is deleted this bit is set when the elastic store fills and a frame is deleted. 1 sb_empt rur/ wc 0 slip buffer empties and a frame is repeated this bit is set when the elastic store empties and a frame is repeated. 0 sb_slip rur/ wc 0 receive slips this bit is set when the slip buffer slips. t able 121: d ata l ink i nterrupt e nable r egister 1 r egister 535 d ata l ink i nterrupt e nable r egister 1 (dlier1) h ex a ddress : 0 x 0b07 b it f unction t ype d efault d escription -o peration
xrt86l30 107 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 123: s lip b uffer i nterrupt e nable r egister (sbier) r egister 537 s lip b uffer i nterrupt e nable r egister (sbier) h ex a ddress : 0 x 0b09 b it f unction t ype d efault d escription -o peration 7 txfull_enb r/w 0 tx interrupt enable bit for slip buf fer full setting this bit enables interrupt when the elastic store fills and a frame is deleted. 6 txempt_enb r/w 0 tx interrupt enable bit for slip buf fer empty setting this bit enables interrupt when the elastic store empties and a frame is repeated. 5 txslip_enb r/w 0 tx interrupt enable bit for slip buf fer slip setting this bit enables interrupt when the slip bu ffer slips. 4-3 reserved - - reserved 2 full_enb r/w 0 interrupt enable bit for slip buffer f ull setting this bit enables interrupt when the elastic store fills and a frame is deleted. 1 empt_enb r/w 0 interrupt enable bit for slip buffer e mpty setting this bit enables interrupt when the elastic store empties and a frame is repeated. 0 slip_enb r/w 0 interrupt enable bit for slip buffer s lip setting this bit enables interrupt when the slip bu ffer slips. t able 124: r eceive l oopback c ode i nterrupt and s tatus r egister (rlcisr) r egister 538 r eceive l oopback c ode i nterrupt and s tatus r egister (rlcisr) h ex a ddress : 0 x 0b0a b it f unction t ype d efault d escription -o peration 7 auxpstat r 0 auxp state this bit indicates the status of receive auxp patte rn. 6 auxpint rur/wc 0 auxp state change interrupt 1 = indicates the receive auxp status has changed. 5 noncrcstat r 0 crc-4-to-non-crc-4 interworking status this bit indicates the status of crc-4 interworking status in modenb mode. 1 = crc-4-to-non-crc-4 interworking is established. 4 noncrcint rur/wc 0 crc-4-to-non-crc-4 interworking in terrupt 1 = indicates the interworking status has changed. 3 rxastat r 0 receive activation status this bit indicates the status of receive activation process. 1 = indi- cates the loopback code activation is received. 2 rxdstat r 0 receive deactivation status this bit indicates the status of receive deactivati on process. 1 = indi- cates the loopback code deactivation is received.
xrt86l30 108 rev. 1.0.1 single t1/e1/j1 framer/liu combo 1 rxaint rur/wc 0 receive activation interrupt 1 = indicates the loopback code activation status h as changed. 0 rxdint rur/wc 0 receive deactivation interrupt 1 = indicates the loopback code deactivation status has changed. t able 125: r eceive l oopback c ode i nterrupt e nable r egister (rlcier) r egister 539 r eceive l oopback c ode i nterrupt e nable r egister (rlcier) h ex a ddress : 0 x 0b0b b it f unction t ype d efault d escription -o peration 6 auxpintenb r/w 0 auxp interrupt enable 1 = enables the receive auxp detect interrupt. 5 reserved - - reserved 4 noncrcenb r/w 0 crc-4 interworking interrupt enable 1 = enables the crc-4-non-crc-4 interworking interr upt. 3-2 reserved - - reserved 1 rxaenb r/w 0 receive activation interrupt enable 1 = enables the loopback code activation interrupt. 0 rxdenb r/w 0 receive deactivation interrupt enable 1 = enables the loopback code deactivation interrup t. t able 126: r eceive sa i nterrupt r egister (rsair) r egister 540 r eceive sa i nterrupt r egister (rsair) h ex a ddress : 0 x 0b0c b it f unction t ype d efault d escription -o peration 7 sa6_1111 r/w 0 debounced sa6 = 1111 received 1 = indicates a debounced sa6 = 1111 has been recei ved. 6 sa6_1110 r/w 0 debounced sa6 = 1110 received 1 = indicates a debounced sa6 = 1111 has been recei ved. 5 sa6_1100 r/w 0 debounced sa6 = 1100 received 1 = indicates a debounced sa6 = 1111 has been recei ved. 4 sa6_1010 r/w 0 debounced sa6 = 1010 received 1 = indicates a debounced sa6 = 1010 has been recei ved. 3 sa6_1000 r/w 0 debounced sa6 = 1000 received 1 = indicates a debounced sa6 = 1111 has been recei ved. 2 sa6_001x r/w 0 debounced sa6 = 001x received 1 = indicates a debounced sa6 = 1111 has been recei ved. t able 124: r eceive l oopback c ode i nterrupt and s tatus r egister (rlcisr) r egister 538 r eceive l oopback c ode i nterrupt and s tatus r egister (rlcisr) h ex a ddress : 0 x 0b0a b it f unction t ype d efault d escription -o peration
xrt86l30 109 single t1/e1/j1 framer/liu combo rev. 1.0.1 1 sa6_other r/w 0 debounced sa6 = other received 1 = indicates a debounced sa6 equals to other combi nation received. 0 sa6_0000 r/w 0 debounced sa6 = 0000 received 1 = indicates a debounced sa6 = 0000 has been recei ved. t able 127: r eceive sa i nterrupt e nable r egister (rsaier) r egister 541 r eceive sa i nterrupt e nable r egister (rsaier) h ex a ddress : 0 x 0b0d b it f unction t ype d efault d escription -o peration 7 sa6_1111_enb r/w 0 debounced sa6 = 1111 received enab le 1 = indicates a debounced sa6 = 1111 has been recei ved. 6 sa6_1110_enb r/w 0 debounced sa6 = 1110 received enab le 1 = enables the generation of an interrupt when a d ebounced sa6 = 1111 has been received. 5 sa6_1100_enb r/w 0 debounced sa6 = 1100 received enab le 1 = enables the generation of an interrupt when a d ebounced sa6 = 1111 has been received. 4 sa6_1010_enb r/w 0 debounced sa6 = 1010 received enab le 1 = enables the generation of an interrupt when a d ebounced sa6 = 1111 has been received. 3 sa6_1000_enb r/w 0 debounced sa6 = 1000 received enab le 1 = enables the generation of an interrupt when a d ebounced sa6 = 1111 has been received. 2 sa6_001x_enb r/w 0 debounced sa6 = 001x received enab le 1 = enables the generation of an interrupt when a d ebounced sa6 = 1111 has been received. 1 sa6_other_enb r/w 0 debounced sa6 = other received en able 1 = enables the generation of an interrupt when a d ebounced sa6 equals to other combinations received. 0 sa6_0000_enb r/w 0 debounced sa6 = 0000 received enab le 1 = enables the generation of an interrupt when a d ebounced sa6 = 0000 has been received. t able 128: e xcessive z ero s tatus r egister r egister 542 e xcessive z ero s tatus r egister (exzsr) h ex a ddress : 0 x 0b0e b it f unction t ype d efault d escription -o peration 0 exz_status rur 0 excessive zero state change 0 = no change in status 1 = change in status has occurred t able 126: r eceive sa i nterrupt r egister (rsair) r egister 540 r eceive sa i nterrupt r egister (rsair) h ex a ddress : 0 x 0b0c b it f unction t ype d efault d escription -o peration
xrt86l30 110 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 129: e xcessive z ero e nable r egister r egister 543 e xcessive z ero e nable r egister (exzer) h ex a ddress : 0 x 0b0f b it f unction t ype d efault d escription -o peration 0 exz_enb r/w 0 excessive zero interrupt enable 0 = disabled 1 = enable excessive zero interrupt generation t able 130: ss7 s tatus r egister for lapd1 r egister 544 ss7 s tatus r egister for lapd1 (ss7sr1) h ex a ddress : 0 x 0b10 b it f unction t ype d efault d escription -o peration 0 ss7_1_status rur 0 ss7 interrupt status for lapd1 0 = no change in status 1 = change in status has occurred t able 131: ss7 e nable r egister for lapd1 r egister 545 ss7 e nable r egister for lapd1 (ss7er1) h ex a ddress : 0 x 0b11 b it f unction t ype d efault d escription -o peration 0 ss7_1_enb r/w 0 ss7 interrupt enable for lapd1 0 = disabled 1 = enable ss7 interrupt generation if more than 27 6 bytes are received within the lapd1 message t able 132: d ata l ink s tatus r egister 2 r egister 546 d ata l ink s tatus r egister 2 (dlsr2) h ex a ddress : 0 x 0b16 b it f unction t ype d efault d escription -o peration 7 msg type rur 0 hdlc2 message type identifier indicates type of data link message received by rx hdlc2 control- ler 0 = bit oriented signaling type data link message r eceived 1 = message oriented signaling type data link messa ge received 6 txsot rur 0 transmit hdlc2 start of transmission inte rrupt status indicates if the transmit hdlc2 start of transmissi on interrupt has occurred since the last read of this register. tran smit hdlc2 con- troller will declare this interrupt when it has sta rted to transmit a data link message. 0 = transmit hdlc2 start of transmission interrupt has not occurred since the last read of this register 1 = transmit hdlc2 start of transmission interrupt has occurred since the last read of this register.
xrt86l30 111 single t1/e1/j1 framer/liu combo rev. 1.0.1 5 rxsot rur 0 receive hdlc2 start of reception interrup t status indicates if the receive hdlc2 start of reception i nterrupt has occurred since the last read of this register. rece ive hdlc2 con- troller will declare this interrupt when it has sta rted to receive a data link message. 0 = receive hdlc2 start of reception interrupt has not occurred since the last read of this register 1 = receive hdlc2 start of reception interrupt has occurred since the last read of this register 4 txeot rur 0 transmit hdlc2 end of transmission interr upt status indicates if the transmit hdlc2 end of transmission interrupt has occurred since the last read of this register. tran smit hdlc2 con- troller will declare this interrupt when it has com pleted its transmis- sion of a data link message. 0 = transmit hdlc2 end of transmission interrupt ha s not occurred since the last read of this register 1 = transmit hdlc2 end of transmission interrupt ha s occurred since the last read of this register 3 rxeot rur 0 receive hdlc2 controller end of reception interrupt status indicates if receive hdlc2 end of reception interru pt has occurred since the last read of this register. receive hdlc2 controller will declare this interrupt once it has completely recei ved a full data link message. 0 = receive hdlc2 end of reception interrupt has no t occurred since the last read of this register 1 = receive hdlc2 end of reception interrupt has oc curred since the last read of this register 2 fcs error rur 0 fcs error interrupt status indicates if the fcs error interrupt has occurred s ince the last read of this register. receive hdlc2 controller will dec lare this interrupt if it detects an error in the most recently receive d data message. 0 = fcs error interrupt has not occurred since last read of this regis- ter 1 = fcs error interrupt has occurred since last rea d of this register t able 132: d ata l ink s tatus r egister 2 r egister 546 d ata l ink s tatus r egister 2 (dlsr2) h ex a ddress : 0 x 0b16 b it f unction t ype d efault d escription -o peration
xrt86l30 112 rev. 1.0.1 single t1/e1/j1 framer/liu combo 1 rx abort rur 0 receipt of abort sequence interrupt st atus indicates if the receipt of abort interrupt has occ urred since last read of this register. receive hdlc2 controller wil l declare this interrupt if it detects a string of seven (7) conse cutive 1s in the incoming data link channel. 0 = receipt of abort sequence interrupt has not occ urred since last read of this register 1 = receipt of abort sequence interrupt has occurre d since last read of this register 0 rxidle rur 0 receipt of idle sequence interrupt statu s indicates if the receipt of idle sequence interrupt has occurred since the last read of this register. the receive h dlc2 controller will declare this interrupt if it detects the flag sequence octet (0x7e) in the incoming data link channel. 0 = receipt of idle sequence interrupt has not occu rred since last read of this register 1 = receipt of idle sequence interrupt has occurred since last read of this register. t able 133: d ata l ink i nterrupt e nable r egister 2 r egister 547 d ata l ink i nterrupt e nable r egister 2 (dlier2) h ex a ddress : 0 x 0b17 b it f unction t ype d efault d escription -o peration 7 reserved - - reserved 6 txsot enb r/w 0 transmit hdlc2 start of transmission interrupt enable 0 = disables the transmit hdlc2 start of transmissi on interrupt 1 = enables the transmit hdlc2 start of transmissio n interrupt 5 rxsot enb r/w 0 receive hdlc2 start of reception inte rrupt enable 0 = disables the receive hdlc2 start of reception i nterrupt 1 = enables the receive hdlc2 start of reception in terrupt 4 txeot enb r/w 0 transmit hdlc2 end of transmission in terrupt enable 0 = disables the transmit hdlc2 end of transmission interrupt 1 = enables the transmit hdlc2 end of transmission interrupt 3 rxeot enb r/w 0 receive hdlc2 end of reception interr upt enable 0 = disables the receive hdlc2 end of reception int errupt 1 = enables the receive hdlc2 end of reception inte rrupt 2 fcs err enb r/w 0 fcs error interrupt enable 0 = disables fcs error interrupt 1 = enables fcs error interrupt t able 132: d ata l ink s tatus r egister 2 r egister 546 d ata l ink s tatus r egister 2 (dlsr2) h ex a ddress : 0 x 0b16 b it f unction t ype d efault d escription -o peration
xrt86l30 113 single t1/e1/j1 framer/liu combo rev. 1.0.1 1 rxabort enb r/w 0 receipt of abort sequence interrupt enable 0 = disables receipt of abort sequence interrupt 1 = enables receive of abort sequence interrupt 0 rxidle enb r/w 0 receipt of idle sequence interrupt e nable 0 = disables receipt of idle sequence interrupt 1 = enables receipt of idle sequence interrupt t able 134: ss7 s tatus r egister for lapd2 r egister 548 ss7 s tatus r egister for lapd2 (ss7sr2) h ex a ddress : 0 x 0b18 b it f unction t ype d efault d escription -o peration 0 ss7_2_status rur 0 ss7 interrupt status for lapd2 0 = no change in status 1 = change in status has occurred t able 135: ss7 e nable r egister for lapd2 r egister 549 ss7 e nable r egister for lapd2 (ss7er2) h ex a ddress : 0 x 0b19 b it f unction t ype d efault d escription -o peration 0 ss7_2_enb r/w 0 ss7 interrupt enable for lapd2 0 = disabled 1 = enable ss7 interrupt generation if more than 27 6 bytes are received within the lapd2 message t able 136: d ata l ink s tatus r egister 3 r egister 550 d ata l ink s tatus r egister 3 (dlsr3) h ex a ddress : 0 x 0b26 b it f unction t ype d efault d escription -o peration 7 msg type rur 0 hdlc3 message type identifier indicates type of data link message received by rx hdlc3 control- ler 0 = bit oriented signaling type data link message r eceived 1 = message oriented signaling type data link messa ge received 6 txsot rur 0 transmit hdlc3 start of transmission inte rrupt status indicates if the transmit hdlc3 start of transmissi on interrupt has occurred since the last read of this register. tran smit hdlc3 con- troller will declare this interrupt when it has sta rted to transmit a data link message. 0 = transmit hdlc3 start of transmission interrupt has not occurred since the last read of this register 1 = transmit hdlc3 start of transmission interrupt has occurred since the last read of this register. t able 133: d ata l ink i nterrupt e nable r egister 2 r egister 547 d ata l ink i nterrupt e nable r egister 2 (dlier2) h ex a ddress : 0 x 0b17 b it f unction t ype d efault d escription -o peration
xrt86l30 114 rev. 1.0.1 single t1/e1/j1 framer/liu combo 5 rxsot rur 0 receive hdlc3 start of reception interrup t status indicates if the receive hdlc3 start of reception i nterrupt has occurred since the last read of this register. rece ive hdlc3 con- troller will declare this interrupt when it has sta rted to receive a data link message. 0 = receive hdlc3 start of reception interrupt has not occurred since the last read of this register 1 = receive hdlc3 start of reception interrupt has occurred since the last read of this register 4 txeot rur 0 transmit hdlc3 end of transmission interr upt status indicates if the transmit hdlc3 end of transmission interrupt has occurred since the last read of this register. tran smit hdlc3 con- troller will declare this interrupt when it has com pleted its transmis- sion of a data link message. 0 = transmit hdlc3 end of transmission interrupt ha s not occurred since the last read of this register 1 = transmit hdlc3 end of transmission interrupt ha s occurred since the last read of this register 3 rxeot rur 0 receive hdlc3 controller end of reception interrupt status indicates if receive hdlc3 end of reception interru pt has occurred since the last read of this register. receive hdlc3 controller will declare this interrupt once it has completely recei ved a full data link message. 0 = receive hdlc3 end of reception interrupt has no t occurred since the last read of this register 1 = receive hdlc3 end of reception interrupt has oc curred since the last read of this register 2 fcs error rur 0 fcs error interrupt status indicates if the fcs error interrupt has occurred s ince the last read of this register. receive hdlc3 controller will dec lare this interrupt if it detects an error in the most recently receive d data message. 0 = fcs error interrupt has not occurred since last read of this regis- ter 1 = fcs error interrupt has occurred since last rea d of this register t able 136: d ata l ink s tatus r egister 3 r egister 550 d ata l ink s tatus r egister 3 (dlsr3) h ex a ddress : 0 x 0b26 b it f unction t ype d efault d escription -o peration
xrt86l30 115 single t1/e1/j1 framer/liu combo rev. 1.0.1 1 rx abort rur 0 receipt of abort sequence interrupt st atus indicates if the receipt of abort interrupt has occ urred since last read of this register. receive hdlc3 controller wil l declare this interrupt if it detects a string of seven (7) conse cutive 1s in the incoming data link channel. 0 = receipt of abort sequence interrupt has not occ urred since last read of this register 1 = receipt of abort sequence interrupt has occurre d since last read of this register 0 rxidle rur 0 receipt of idle sequence interrupt statu s indicates if the receipt of idle sequence interrupt has occurred since the last read of this register. the receive h dlc2 controller will declare this interrupt if it detects the flag sequence octet (0x7e) in the incoming data link channel. 0 = receipt of idle sequence interrupt has not occu rred since last read of this register 1 = receipt of idle sequence interrupt has occurred since last read of this register. t able 137: d ata l ink i nterrupt e nable r egister 3 r egister 551 d ata l ink i nterrupt e nable r egister 3 (dlier3) h ex a ddress : 0 x 0b27 b it f unction t ype d efault d escription -o peration 7 reserved - - reserved 6 txsot enb r/w 0 transmit hdlc3 start of transmission interrupt enable 0 = disables the transmit hdlc3 start of transmissi on interrupt 1 = enables the transmit hdlc3 start of transmissio n interrupt 5 rxsot enb r/w 0 receive hdlc3 start of reception inte rrupt enable 0 = disables the receive hdlc3 start of reception i nterrupt 1 = enables the receive hdlc3 start of reception in terrupt 4 txeot enb r/w 0 transmit hdlc3 end of transmission in terrupt enable 0 = disables the transmit hdlc3 end of transmission interrupt 1 = enables the transmit hdlc3 end of transmission interrupt 3 rxeot enb r/w 0 receive hdlc3 end of reception interr upt enable 0 = disables the receive hdlc3 end of reception int errupt 1 = enables the receive hdlc3 end of reception inte rrupt 2 fcs err enb r/w 0 fcs error interrupt enable 0 = disables fcs error interrupt 1 = enables fcs error interrupt t able 136: d ata l ink s tatus r egister 3 r egister 550 d ata l ink s tatus r egister 3 (dlsr3) h ex a ddress : 0 x 0b26 b it f unction t ype d efault d escription -o peration
xrt86l30 116 rev. 1.0.1 single t1/e1/j1 framer/liu combo 1 rxabort enb r/w 0 receipt of abort sequence interrupt enable 0 = disables receipt of abort sequence interrupt 1 = enables receive of abort sequence interrupt 0 rxidle enb r/w 0 receipt of idle sequence interrupt e nable 0 = disables receipt of idle sequence interrupt 1 = enables receipt of idle sequence interrupt t able 138: ss7 s tatus r egister for lapd3 r egister 552 ss7 s tatus r egister for lapd3 (ss7sr3) h ex a ddress : 0 x 0b28 b it f unction t ype d efault d escription -o peration 0 ss7_3_status rur 0 ss7 interrupt status for lapd3 0 = no change in status 1 = change in status has occurred t able 139: ss7 e nable r egister for lapd3 r egister 553 ss7 e nable r egister for lapd3 (ss7er3) h ex a ddress : 0 x 0b29 b it f unction t ype d efault d escription -o peration 0 ss7_3_enb r/w 0 ss7 interrupt enable for lapd3 0 = disabled 1 = enable ss7 interrupt generation if more than 27 6 bytes are received within the lapd3 message t able 140: c ustomer i nstallation a larm s tatus r egister r egister 554 c ustomer i nstallation a larm s tatus r egister (ciasr) h ex a ddress : 0 x 0b40 b it f unction t ype d efault d escription -o peration [7:6] reserved - - these bits are reserved 5 rxais-ci_state r/w 0 rx ais-ci state 0 = no ais-ci state detected 1 = ais-ci state detected 4 rxrai-ci_state r/w 0 rx rai-ci state 0 = no rai-ci state detected 1 = rai-ci state detected [3:2] reserved - - these bits are reserved t able 137: d ata l ink i nterrupt e nable r egister 3 r egister 551 d ata l ink i nterrupt e nable r egister 3 (dlier3) h ex a ddress : 0 x 0b27 b it f unction t ype d efault d escription -o peration
xrt86l30 117 single t1/e1/j1 framer/liu combo rev. 1.0.1 1 rxais-ci rur 0 rx ais-ci state change 0 = no change in status 1 = change of status has occurred 0 rxrai-ci rur 0 rx rai-ci state change 0 = no change in status 1 = change of status has occurred t able 141: c ustomer i nstallation a larm s tatus r egister r egister 555 c ustomer i nstallation a larm i nterrupt e nable r egister (ciaier) h ex a ddress : 0 x 0b41 b it f unction t ype d efault d escription -o peration 1 rxais-ci_enb r/w 0 rx ais-ci interrupt generation ena ble 0 = disabled 1 - enable rx ais-ci interrupt generation 0 rxrai-ci_enb r/w 0 rx rai-ci interrupt generation ena ble 0 = disabled 1 - enable rx rai-ci interrupt generation t able 140: c ustomer i nstallation a larm s tatus r egister r egister 554 c ustomer i nstallation a larm s tatus r egister (ciasr) h ex a ddress : 0 x 0b40 b it f unction t ype d efault d escription -o peration
xrt86l30 118 rev. 1.0.1 single t1/e1/j1 framer/liu combo 3.5 programming the line interface unit (liu section ) control registers t able 142: m icroprocessor r egister #556 b it d escription r egister a ddress 0 x 0f00 h c hannel 0 f unction r egister t ype r eset v alue b it # n ame d7 reserved this bit is not used r/w 0 d6 reserved this bit is not used r/w d5 rxon_n receiver on: writing a 1 into this bit location turns on the receive section of channel n. writing a 0 shuts o ff the receiver section of channel n. r/w 0 d4 eqc4_n equalizer control bit 4: this bit together with eqc[3:0] are used for controlling transmit pulse shaping, transm it line build- out (lbo) and receive monitoring for either t1 or e 1 modes of operation. see table . r/w 0 d3 eqc3_n equalizer control bit 3: see bit d4 description for function of this bit r/w 0 d2 eqc2_n equalizer control bit 2: see bit d4 description for function of this bit r/w 0 d1 eqc1_n equalizer control bit 1: see bit d4 description for function of this bit r/w 0 d0 eqc0_n equalizer control bit 0: see bit d4 description for function of this bit r/w 0 t able 143: e qualizer c ontrol and t ransmit l ine b uild o ut eqc[4:0] t1/e1 m ode /r eceive s ensitivity t ransmit lbo c able 0x00h t1 long haul/36db 0db 100 w tp 0x01h t1 long haul/36db -7.5db 100 w tp 0x02h t1 long haul/36db -15db 100 w tp 0x03h t1 long haul/36db -22.5db 100 w tp 0x04h t1 long haul/45db 0db 100 w tp 0x05h t1 long haul/45db -7.5db 100 w tp 0x06h t1 long haul/45db -15db 100 w tp 0x07h t1 long haul/45db -22.5db 100 w tp 0x08h t1 short haul/15db 0 to 133 feet (0.6db) 100 w tp 0x09h t1 short haul/15db 133 to 266 feet (1.2db) 100 w tp 0x0ah t1 short haul/15db 266 to 399 feet (1.8db) 100 w tp 0x0bh t1 short haul/15db 399 to 533 feet (2.4db) 100 w tp 0x0ch t1 short haul/15db 533 to 655 feet (3.0db) 100 w tp
xrt86l30 119 single t1/e1/j1 framer/liu combo rev. 1.0.1 0x0dh t1 short haul/15db arbitrary pulse 100 w tp 0x0eh t1 gain mode/29db 0 to 133 feet (0.6db) 100 w tp 0x0fh t1 gain mode/29db 133 to 266 feet (1.2db) 100 w tp 0x10h t1 gain mode/29db 266 to 399 feet (1.8db) 100 w tp 0x11h t1 gain mode/29db 399 to 533 feet (2.4db) 100 w tp 0x12h t1 gain mode/29db 533 to 655 feet (3.0db) 100 w tp 0x13h t1 gain mode/29db arbitrary pulse 100 w tp 0x14h t1 gain mode/29db 0db 100 w tp 0x15h t1 gain mode/29db -7.5db 100 w tp 0x16h t1 gain mode/29db -15db 100 w tp 0x17h t1 gain mode/29db -22.5db 100 w tp 0x18h e1 long haul/36db itu g.703 75 w coax 0x19h e1 long haul/36db itu g.703 120 w tp 0x1ah e1 long haul/45db itu g.703 75 w coax 0x1bh e1 long haul/45db itu g.703 120 w tp 0x1ch e1 short haul/15db itu g.703 75 w coax 0x1dh e1 short haul/15db itu g.703 120 w tp 0x1eh e1 gain mode/29db itu g.703 75 w coax 0x1fh e1 gain mode/29db itu g.703 120 w tp t able 143: e qualizer c ontrol and t ransmit l ine b uild o ut eqc[4:0] t1/e1 m ode /r eceive s ensitivity t ransmit lbo c able
xrt86l30 120 rev. 1.0.1 single t1/e1/j1 framer/liu combo
xrt86l30 121 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 144: m icroprocessor r egister #557 b it d escription r egister a ddress 0 x 0f01 h c hannel _0 f unction r egister t ype r eset v alue b it # n ame d7 rxtsel_n receiver termination select: in host mode, this bit is used to select between the internal termination and high impedance modes for the receiver according to the following t able; r/w 0 d6 txtsel_n transmit termination select: in host mode, this bit is used to select between the internal termination and high impedance modes for the transmitter according to the followin g table; r/w 0 d5 tersel1_n termination impedance select1: in host mode and in internal termination mode, (txtsel = 1 and rxtsel = 1) tersel[1:0] control the transmit and receive termination impedance according to the foll owing table; in the internal termination mode, the receiver term ination of each receiver is realized completely by internal re sistors or by the combination of internal and one fixed external resistor. in the internal termination mode, the transmitter o utput should be ac coupled to the transformer. r/w 0 d4 tersel0_n termination impedance select bit 0: r/w 0 d3 rxjasel_n receive jitter attenuator enable the bit is used to enable the receive jitter attenu ator. 0 = disabled 1 = enable the receive jitter attenuator r/w 0 d2 txjasel_n transmit jitter attenuator enable the bit is used to enable the transmit jitter atten uator. 0 = disabled 1 = enable the transmit jitter attenuator r/w 0 rxtsel rx termination 0 1 "high" impedance internal txtsel tx termination 0 1 "high" impedance internal tersel1 tersel0 0 0 0 1 1 0 1 1 termination 100 w 110 w 75 w 120 w
xrt86l30 122 rev. 1.0.1 single t1/e1/j1 framer/liu combo d1 jabw_n jitter attenuator bandwidth select: in e1 mode, set this bit to 1 to select a 1.5hz bandwidth for the jitter a ttenuator. the fifo length will be automatically set to 64 bits. s et this bit to 0 to select 10hz bandwidth for the jitter attenua tor in e1 mode. in t1 mode the jitter attenuator bandwidth is perma- nently set to 3hz, and the state of this bit has no effect on the bandwidth. r/w 0 d0 fifos_n fifo size select: see table of bit d1 above for the function of this bit. r/w 0 t able 144: m icroprocessor r egister #557 b it d escription r egister a ddress 0 x 0f01 h c hannel _0 f unction r egister t ype r eset v alue b it # n ame 0 1 0 1 0 1 0 1 fifos_n bit d0 0 0 1 1 0 0 1 1 jabw bit d1 t1 t1 t1 t1 e1 e1 e1 e1 mode 32 64 32 64 32 64 64 64 fifo size 3 3 3 3 10 10 1.5 1.5 ja b-w hz
xrt86l30 123 single t1/e1/j1 framer/liu combo rev. 1.0.1
xrt86l30 124 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 145: m icroprocessor r egister #558 b it d escription r egister a ddress 0 x 0f02 h c hannel _0 f unction r egister t ype r eset v alue b it # n ame d7 invqrss_n invert qrss pattern: when tqrss is active, writing a 1 to this bit inverts the polarity of transmitted qrss p attern. writing a 0 sends the qrss pattern with no inversion. r/w 0 d6 txtest2_n transmit test pattern bit 2 : this bit together with txtest1 and txtest0 are used to generate and transmit test patterns according to the following table: tdqrss (transmit/detect quasi-random signal): this condition when activated enables quasi-random signa l source generation and detection for the selected ch annel num- ber n. in a t1 system qrss pattern is a 2 20 -1 pseudo-random bit sequence (prbs) with no more than 14 consecutiv e zeros. in a e1 system, qrss is a 2 15 -1 prbs pattern. taos (transmit all ones): activating this condition enables the transmission of an all ones pattern from the se lected channel number n. tluc (transmit network loop-up code): activating this condition enables the network loop-up code of 0000 1 to be transmitted to the line for the selected channel nu mber n. when network loop-up code is being transmitted, the xrt86l30 will ignore the automatic loop-code detect ion and remote loop-back activation (nlcde1 =1, nlcde0 = 1, if activated) in order to avoid activating remote digi tal loop- back automatically when the remote terminal respond s to the loop-back request. tldc (transmit network loop-down code): activating this condition enables the network loop-down code of 00 1 to be transmitted to the line for the selected channel nu mber n. r/w 0 d5 txtest1_n transmit test pattern bit 1: see description of bit d6 for the function of this bit. r/w 0 d4 txtest0_n transmit test pattern bit 0: see description of bit d6 for the function of this bit. r/w 0 d3 txon_n transmitter on: writing a 1 into this bit location turns on the transmit section of channel n. writing a 0 shuts off the trans- mit section of channel n. in this mode, ttip_n and tring_n driver outputs will be tri-stated for power reducti on or redun- dancy applications. r/w 0 0 0 0 1 1 0 1 1 1 1 1 1 x x 0 no pattern tdqrss taos tluc test pattern tldc txtest1 txtest0 txtest2
xrt86l30 125 single t1/e1/j1 framer/liu combo rev. 1.0.1 d2 loop2_n loop-back control bit 2: this bit together with the loop1 and loop0 bits control the loop-back modes of the l iu sec- tion of the chip according to the following table: d1 loop1_n loop-back control bit 1: see description of bit d2 for the function of this bit. r/w 0 d0 loop0_n loop-back control bit 0: see description of bit d2 for the function of this bit. r/w 0 t able 145: m icroprocessor r egister #558 b it d escription r egister a ddress 0 x 0f02 h c hannel _0 f unction r egister t ype r eset v alue b it # n ame loop2 0 1 1 1 1 loop1 x 0 0 1 1 loop0 x 0 1 0 1 loop-back mode no loop-back dual loop-back analog loop-back remote loop-back digital loop-back
xrt86l30 126 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 146: m icroprocessor r egister #559 b it d escription r egister a ddress 0 x 0f03 h c hannel _0 f unction r egister t ype r eset v alue bit # n ame d7 nlcde1_n network loop code detection enable bit 1: this bit together with nlcde0_n control the loop-co de detec- tion of each channel. when nlcde1 =0 and nlcde0 = 1 or nlcde1 = 1 a nd nlcde0 = 0, the chip is manually programmed to mo nitor the receive data for the loop-up or loop-down code respec- tively.when the presence of the 00001 or 001 pa ttern is detected for more than 5 seconds, the status of the nlcd bit is set to 1 and if the nlcd interrupt is enabled, an interrupt is initiated.the host has the option to control the lo op-back function manually. setting the nlcde1 = 1 and nlcde0 = 1 enables t he automatic loop-code detection and remote loop-back acti- vation mode. as this mode is initiated, the state o f the nlcd interface bit is reset to 0 and the chip is progr ammed to mon- itor the receive data for the loop-up code. if the 00001 pat- tern is detected for longer than 5 seconds, the nlc d bit is set 1, remote loop-back is activated and the chip is automati- cally programmed to monitor the receive data for th e loop- down code. the nlcd bit stays set even after the ch ip stops receiving the loop-up code. the remote loop-back co ndition is removed when the chip receives the loop-down cod e for more than 5 seconds or if the automatic loop-code d etection mode is terminated. r/w 0 d6 nlcde0_n network loop code detection enable bit 0: see description of d7 for function of this bit. r/w 0 d5 reserved this bit is not used r/w 0 nlcde1 nlcde0 0 0 0 1 1 0 1 1 function disable loop-code detection detect loop-up code in receive data detect loop-down code in receive data automatic loop-code detection
xrt86l30 127 single t1/e1/j1 framer/liu combo rev. 1.0.1 d4 rxres1_n receive external resistor control pin 1: in host mode, this bit along with the rxres0_n bit selects the value of th e external receive fixed resistor according to the following t able; r/w 0 d3 rxres0_n receive external resistor control pin 0: for function of this bit see description of d4 the rxres1_n bit. r/w 0 d2 insbpv_n insert bipolar violation: when this bit transitions from 0 to 1, a bipolar violation is inserted in the transmi tted data stream of the selected channel number n. bipolar vi olation can be inserted either in the qrss pattern, or input da ta when operating in single-rail mode. the state of this bi t is sampled on the rising edge of the respective tclk_n. n ote : to ensure the insertion of a bipolar violation, a 0 should be written in this bit location before writi ng a 1. r/w 0 d1 insber_n insert bit error: with tdqrss enabled, when this bit transi- tions from 0 to 1, a bit error will be inserted in the transmit- ted qrss pattern of the selected channel number n. the state of this bit is sampled on the rising edge of the re spective tclk_n. n ote : to ensure the insertion of bit error, a 0 should be written in this bit location before writing a 1. r/w 0 d0 reserved this bit is not used r/w 0 t able 147: m icroprocessor r egister #560 b it d escription r egister a ddress 0 x 0f04 h c hannel _0 f unction r egister t ype r eset v alue bit # n ame d7 reserved this bit is not used ro 0 d6 dmoie_n dmo interrupt enable: writing a 1 to this bit enables dmo interrupt generation, writing a 0 masks it. r/w 0 d5 flsie_n fifo limit status interrupt enable: writing a 1 to this bit enables interrupt generation when the fifo limit is within to 3 bits, writing a 0 to masks it. r/w 0 d4 lcvie_n line code violation interrupt enable: writing a 1 to this bit enables line code violation interrupt generation, w riting a 0 masks it. r/w 0 t able 146: m icroprocessor r egister #559 b it d escription rxre s1_n 0 0 r equired fixed external rx resistor n o external fixed r esistor 240 w ww w rxre s0_n 0 1 1 1 210 w ww w 150 w ww w 0 1
xrt86l30 128 rev. 1.0.1 single t1/e1/j1 framer/liu combo d3 nlcdie_n network loop-code detection interrupt enable: writing a 1 to this bit enables network loop-code detection interrupt generation, writing a 0 masks it. r/w 0 d2 aisdie_n ais interrupt enable: writing a 1 to this bit enables alarm indication signal detection interrupt generation, w riting a 0 masks it. r/w 0 d1 rlosie_n receive loss of signal interrupt enable: writing a 1 to this bit enables loss of receive signal interrupt genera tion, writing a 0 masks it. r/w 0 d0 qrpdie_n qrss pattern detection interrupt enable: writing a 1 to this bit enables qrss pattern detection interrupt g eneration, writing a 0 masks it. r/w 0 t able 148: m icroprocessor r egister #561 b it d escription r egister a ddress 0 x 0f05 h c hannel _0 f unction r egister t ype r eset v alue bit # n ame d7 reserved ro 0 d6 dmo_n driver monitor output: this bit is set to a 1 to indicate transmit driver failure is detected. the value of t his bit is based on the current status of dmo for the corresponding channel. if the dmoie bit is enabled, any transition on this bi t will gener- ate an interrupt. ro 0 d5 fls_n fifo limit status: this bit is set to a 1 to indicate that the jit- ter attenuator read/write fifo pointers are within +/- 3 bits. if the flsie bit is enabled, any transition on this bi t will generate an interrupt. ro 0 d4 lcv_n line code violation: this bit is set to a 1 to indicate that the receiver of channel n is currently detecting a line code viola- tion or an excessive number of zeros in the b8zs or hdb3 modes. if the lcvie bit is enabled, any transition on this bit will generate an interrupt. ro 0 t able 147: m icroprocessor r egister #560 b it d escription
xrt86l30 129 single t1/e1/j1 framer/liu combo rev. 1.0.1 d3 nlcd_n network loop-code detection: this bit operates differently in the manual or the automatic network loop-code detection modes. in the manual loop-code detection mode , (nlcde1 = 0 and nlcde0 = 1 or nlcde1 = 1 and nlcde0 = 0) this bit gets set to 1 as soon as the loop-up (00001 ) or loop- down (001) code is detected in the receive data f or longer than 5 seconds. the nlcd bit stays in the 1 state for as long as the chip detects the presence of the loop-code i n the receive data and it is reset to 0 as soon as it s tops receiving it. in this mode, if the nlcd interrupt is enabled, the chip will initiate an interrupt on every transition of the nl cd. when the automatic loop-code detection mode, (nlcde1 = 1 and nlcde0 =1) is initiated, the state of t he nlcd interface bit is reset to 0 and the chip is progr ammed to mon- itor the receive input data for the loop-up code. t his bit is set to a 1 to indicate that the network loop code is detected for more than 5 seconds. simultaneously the remote loop -back condition is automatically activated and the chip i s pro- grammed to monitor the receive data for the network loop down code. the nlcd bit stays in the 1 state for as long as the remote loop-back condition is in effect even if the chip stops receiving the loop-up code. remote loop-back is removed if the chip detects the 001 pattern for l onger than 5 seconds in the receive data.detecting the 001 pat tern also results in resetting the nlcd interface bit and ini tiating an interrupt provided the nlcd interrupt enable bit is active. when programmed in automatic detection mode, the nlcd interface bit stays high for the entire time the remote loop-back is active and initiate an interrupt anyti me the status of the nlcd bit changes. in this mode, the host can monitor the state of the nlcd bit to determine if the remot e loop- back is activated. ro 0 d2 aisd_n alarm indication signal detect: this bit is set to a 1 to indi- cate all ones signal is detected by the receiver. t he value of this bit is based on the current status of alarm in dication signal detector of channel n. if the aisdie bit is enabled , any transi- tion on this bit will generate an interrupt. ro 0 d1 rlos_n receive loss of signal: this bit is set to a 1 to indicate that the receive input signal is lost. the value of this bit is based on the current status of the receive input signal of c hannel n. if the rlosie bit is enabled, any transition on this bit w ill generate an interrupt. ro 0 d0 qrpd_n quasi-random pattern detection: this bit is set to a 1 to indicate the receiver is currently in synchronizati on with qrss pattern. the value of this bit is based on the curr ent status of quasi-random pattern detector of channel n. if the qrpdie bit is enabled, any transition on this bit will generat e an interrupt. ro 0 t able 148: m icroprocessor r egister #561 b it d escription
xrt86l30 130 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 149: m icroprocessor r egister #562 b it d escription r egister a ddress 0 x 0f06 h c hannel _0 f unction r egister t ype r eset v alue bit # n ame d7 reserved ro 0 d6 dmois_n driver monitor output interrupt status: this bit is set to a 1 every time the dmo status has changed since las t read. n ote : this bit is reset upon read. rur 0 d5 flsis_n fifo limit interrupt status: this bit is set to a 1 every time when fifo limit (read/write pointer with +/- 3 bits apart) sta- tus has changed since last read. n ote : this bit is reset upon read. rur 0 d4 lcvis_n line code violation interrupt status: this bit is set to a 1 every time when lcv status has changed since last r ead. n ote : this bit is reset upon read. rur 0 d3 nlcdis_n network loop-code detection interrupt status: this bit is set to a 1 every time when nlcd status has change d since last read. n ote : this bit is reset upon read. rur 0 d2 aisdis_n ais detection interrupt status: this bit is set to a 1 every time when aisd status has changed since last read. n ote : this bit is reset upon read. rur 0 d1 rlosis_n receive loss of signal interrupt status: this bit is set to a 1 every time rlos status has changed since last r ead. n ote : this bit is reset upon read. rur 0 d0 qrpdis_n quasi-random pattern detection interrupt status: this bit is set to a 1 every time when qrpd status has cha nged since last read. n ote : this bit is reset upon read. rur 0 t able 150: m icroprocessor r egister #563 b it d escription r egister a ddress 0 x 0f07 h c hannel _0 f unction r egister t ype r eset v alue bit # n ame d7 reserved ro 0 d6 reserved ro 0 d5 clos5_n cable loss bit 5: clos[5:0]_n are the six bit receive selec- tive equalizer setting which is also a binary word that repre- sents the cable attenuation indication within 1db. clos5_n is the most significant bit (msb) and clos0_n is th e least sig- nificant bit (lsb). ro 0 d4 clos4_n cable loss bit 4: see description of d5 for function of this bit. ro 0 d3 clos3_n cable loss bit 3: see description of d5 for function of this bit. ro 0
xrt86l30 131 single t1/e1/j1 framer/liu combo rev. 1.0.1 d2 clos2_n cable loss bit 2: see description of d5 for function of this bit. ro 0 d1 clos1_n cable loss bit 1: see description of d5 for function of this bit. ro 0 d0 clos0_n cable loss bit 0: see description of d5 for function of this bit. ro 0 t able 151: m icroprocessor r egister #564 b it d escription r egister a ddress 0 x 0f08 h c hannel _0 f unction r egister t ype r eset v alue bit # n ame d7 reserved r/w 0 d6-d0 b6s1_n - b0s1_n arbitrary transmit pulse shape, segment 1:the shape of each channel's transmitted pulse can be made independent ly user programmable by selecting arbitrary pulse mode. the arbi- trary pulse is divided into eight time segments who se com- bined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the n th chan- nel's arbitrary pulse during the first time segment . b6s1_n- b0s1_n is in signed magnitude format with b6s1_n as the sign bit and b0s1_n as the least significant bit (l sb). r/w 0 t able 152: m icroprocessor r egister #565 b it d escription r egister a ddress 0 x 0f09 h c hannel _0 f unction r egister t ype r eset v alue bit # n ame d7 reserved r/w 0 d6-d0 b6s2_n - b0s2_n arbitrary transmit pulse shape, segment 2 the shape of each channel's transmitted pulse can b e made independently user programmable by selecting arbit rary pulse mode. the arbitrary pulse is divided into e ight time segments whose combined duration is equal to one pe riod of mclk. this 7 bit number represents the amplitude of the n th chan- nel's arbitrary pulse during the second time segmen t. b6s2_n- b0s2_n is in signed magnitude format with b6s2_n as the sign bit and b0s2_n as the least significant bit (l sb). r/w 0 t able 150: m icroprocessor r egister #563 b it d escription
xrt86l30 132 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 153: m icroprocessor r egister #566 b it d escription r egister a ddress 0 x 0f0a h c hannel _0 f unction r egister t ype r eset v alue bit # n ame d7 reserved r/w 0 d6-d0 b6s3_n - b0s3_n arbitrary transmit pulse shape, segment 3 the shape of each channel's transmitted pulse can b e made independently user programmable by selecting arbit rary pulse mode. the arbitrary pulse is divided into e ight time segments whose combined duration is equal to one pe riod of mclk. this 7 bit number represents the amplitude of the n th chan- nel's arbitrary pulse during the third time segment . b6s3_n- b0s3_n is in signed magnitude format with b6s3_n as the sign bit and b0s3_n as the least significant bit (l sb). r/w 0 t able 154: m icroprocessor r egister #567 b it d escription r egister a ddress 0 x 0f0b h c hannel _0 f unction r egister t ype r eset v alue bit # n ame d7 reserved r/w 0 d6-d0 b6s4_n - b0s4_n arbitrary transmit pulse shape, segment 4 the shape of each channel's transmitted pulse can b e made independently user programmable by selecting arbit rary pulse mode. the arbitrary pulse is divided into e ight time segments whose combined duration is equal to one pe riod of mclk. this 7 bit number represents the amplitude of the n th chan- nel's arbitrary pulse during the fourth time segmen t. b6s4_n- b0s4_n is in signed magnitude format with b6s4_n as the sign bit and b0s4_n as the least significant bit (l sb). r/w 0
xrt86l30 133 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 155: m icroprocessor r egister #568 b it d escription r egister a ddress 0 x 0f0c h c hannel _0 f unction r egister t ype r eset v alue bit # n ame d7 reserved r/w 0 d6-d0 b6s5_n - b0s5_n arbitrary transmit pulse shape, segment 5 the shape of each channel's transmitted pulse can b e made independently user programmable by selecting arbit rary pulse mode. the arbitrary pulse is divided into e ight time segments whose combined duration is equal to one pe riod of mclk. this 7 bit number represents the amplitude of the n th chan- nel's arbitrary pulse during the fifth time segment . b6s5_n- b0s5_n is in signed magnitude format with b6s5_n as the sign bit and b0s5_n as the least significant bit (l sb). r/w 0 t able 156: m icroprocessor r egister #569 b it d escription r egister a ddress 0 x 0f0d h c hannel _0 f unction r egister t ype r eset v alue bit # n ame d7 reserved r/w 0 d6-d0 b6s6_n - b0s6_n arbitrary transmit pulse shape, segment 6 the shape of each channel's transmitted pulse can b e made independently user programmable by selecting arbit rary pulse mode. the arbitrary pulse is divided into e ight time segments whose combined duration is equal to one pe riod of mclk. this 7 bit number represents the amplitude of the n th chan- nel's arbitrary pulse during the sixth time segment . b6s6_n- b0s6_n is in signed magnitude format with b6s6_n as the sign bit and b0s6_n as the least significant bit (l sb). r/w 0
xrt86l30 134 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 157: m icroprocessor r egister #570 b it d escription r egister a ddress 0 x 0f0e h c hannel _0 f unction r egister t ype r eset v alue bit # n ame d7 reserved r/w 0 d6-d0 b6s7_n - b0s7_n arbitrary transmit pulse shape, segment 7 the shape of each channel's transmitted pulse can b e made independently user programmable by selecting arbit rary pulse mode. the arbitrary pulse is divided into e ight time segments whose combined duration is equal to one pe riod of mclk. this 7 bit number represents the amplitude of the n th chan- nel's arbitrary pulse during the seventh time segme nt. b6s7_n-b0s7_n is in signed magnitude format with b6 s7_n as the sign bit and b0s7_n as the least significant bit (lsb). r/w 0 t able 158: m icroprocessor r egister #571 b it d escription r egister a ddress 0 x 0f0f h c hannel _0 f unction r egister t ype r eset v alue bit # n ame d7 reserved r/w 0 d6-d0 b6s8_n - b0s8_n arbitrary transmit pulse shape, segment 8 the shape of each channel's transmitted pulse can b e made independently user programmable by selecting arbit rary pulse mode. the arbitrary pulse is divided into e ight time segments whose combined duration is equal to one pe riod of mclk. this 7 bit number represents the amplitude of the n th chan- nel's arbitrary pulse during the eighth time segmen t. b6s8_n- b0s8_n is in signed magnitude format with b6s8_n as the sign bit and b0s8_n as the least significant bit (l sb). r/w 0
xrt86l30 135 single t1/e1/j1 framer/liu combo rev. 1.0.1 global control registers t able 159: m icroprocessor r egister #700 b it d escription - g lobal r egister 0 r egister a ddress 0 x 0fe0 h n ame f unction r egister t ype r eset v alue bit # d7 reserved this bit is not used r/w 0 d6 ataos automatic transmit all ones upon rlos: writing a 1 to this bit enables the automatic transmission of all "ones" data to the line for the channel that detects an rlos co ndition. writing a 0 disables this feature. r/w 0 d5 reserved this bit is not used r/w 0 d4 reserved this bit is not used r/w 0 d3 reserved this bit is not used r/w 0 d2 reserved this bit is not used 0 d1 gie global interrupt enable: writing a 1 to this bit globally enables interrupt generation for all channels. writing a 0 disables interrupt generation. r/w 0 d0 sreset software reset m p registers: writing a 1 to this bit longer than 10s initiates a device reset through the micr oprocessor interface. all internal circuits are placed in the reset state with this bit set to a 1 except the microprocessor reg ister bits. r/w 0 t able 160: m icroprocessor r egister #701, b it d escription - g lobal r egister 1 r egister a ddress 0x0fe1h n ame f unction r egister t ype r eset v alue bit # d7 reserved r/w 0 d6 reserved r/w 0 d5 d4 guage1 guage0 wire gauge selector bit 1: this bit together with bit d6 are used to select wi re gauge size as shown in the table below. r/w 0 0 d3 reserved this bit is not used r/w 0 gauge1 0 1 1 0 gauge0 0 1 0 1 wire size 22 and 24 gauge 26 gauge 24 gauge 22 gauge
xrt86l30 136 rev. 1.0.1 single t1/e1/j1 framer/liu combo d2 rxmute receive output mute: writing a 1 to this bit, mutes receive outputs at the framer block to a 0 state for any channel that detects an rlos condition. n ote : the receive clock is not muted. r/w 0 d1 exlos extended los: writing a 1 to this bit extends the number of zeros at the receive input of each channel before r los is declared to 4096 bits. writing a 0 reverts to the normal mode (175+75 bits for t1 and 32 bits for e1). r/w 0 d0 ict in-circuit-testing: writing a 1 to this bit configures all the output pins of the chip in high impedance mode for in-circuit- testing. r/w 0 t able 161: m icroprocessor r egister #702, b it d escription - g lobal r egister 2 r egister a ddress 0x0fe2h n ame f unction r egister t ype r eset v alue bit # d7 reserved this bit is not used r/w 0 d6 reserved this bit is not used r/w 0 d5-d0 reserved this bit is not used r/w 0 t able 162: m icroprocessor r egister #703, b it d escription - g lobal r egister 3 r egister a ddress 0x0fe4h n ame f unction r egister t ype r eset v alue bit # d7 d6 mclknt11 mclknt10 master t1 output clock reference these two bits are used to select the programmable output clock reference for t1mclknout. 00 = 1.544mhz 01 = 3.088mhz 10 = 6.176mhz 11 = 12.352mhz r/w 0 0 d5 d4 mclkne11 mclkne10 master e1 output clock reference these two bits are used to select the programmable output clock reference for e1mclknout. 00 = 2.048mhz 01 = 4.096mhz 10 = 8.192mhz 11 = 16.384mhz r/w 0 0 d3 reserved this bit is not used. r/w 0 d2 reserved this bit is not used. r/w 0 t able 160: m icroprocessor r egister #701, b it d escription - g lobal r egister 1
xrt86l30 137 single t1/e1/j1 framer/liu combo rev. 1.0.1 d1 reserved this bit is not used. r/w 0 d0 reserved this bit is not used. r/w 0 t able 163: m icroprocessor r egister #704, b it d escription - g lobal r egister 4 r egister a ddress 0x0fe9h n ame f unction r egister t ype r eset v alue bit # d7 reserved this bit is not used. r/w 0 d6 reserved this bit is not used. r/w 0 d5 reserved this bit is not used. r/w 0 d4 reserved this bit is not used. r/w 0 d3 d2 d1 d0 clksel3 clksel2 clksel1 clksel0 clock select input clksel[3:0] is used to select the input clock sourc e to be used as the internal timing reference for mclkin. 0000 = 2.048mhz 0001 = 1.544mhz 0010 = 8khz 0011 = 16khz 0100 = 56khz 0101 = 64khz 0110 = 128khz 0111 = 256khz 1000 = 4.096mhz 1001 = 3.088mhz 1010 = 8.192mhz 1011 = 6.176mhz 1100 = 16.384mhz 1101 = 12.352mhz 1110 = 2.048mhz 1111 = 1.544mhz r/w 0 00 0 t able 162: m icroprocessor r egister #703, b it d escription - g lobal r egister 3
xrt86l30 138 rev. 1.0.1 single t1/e1/j1 framer/liu combo 3.6 the interrupt structure within the framer the xrt86l30 framer is equipped with a sophisticate d interrupt servicing structure. this interrupt str ucture includes an interrupt request output pin int , numerous interrupt enable registers and numerous interrupt status registers. the interrupt servicing structure, within the xrt86 l30 framer contains three levels of hierarchy: the framer level the block level the source level. the framer interrupt structure has been carefully d esigned to allow the user to quickly determine the exact source of this interrupt (with minimal latency) whi ch will aid the mc/mp in determining the which inte rrupt service routine to call up in order to eliminate or properly respond to the condition(s) causing the i nterrupt. the xrt86l30 framer comes equipped with registers t o support the servicing of this wide array of poten tial "interrupt request" sources. table 164 lists the possible conditions that can generate in terrupts. general flow of interrupt servicing when any of the conditions presented in table 164 occur, (if their interrupt is enabled), then the f ramer generates an interrupt request to the mp/mc by asse rting the active-low interrupt request output pin, int . shortly after the local mc/mp has detected the acti vated int signal, it will enter into the appropriate user- supplied interrupt service routine. the first task for the mp/mc, while running this interrupt service routine, may be to isolate the source of the interrupt request d own to the device level (e.g, the framer ic), if mu ltiple peripheral ics exist in the user's system. however, once the interrupting peripheral device has been i dentified, t able 164: l ist of the p ossible c onditions that can g enerate i nterrupts , in each f ramer i nterrupt b lock i nterrupting c ondition framer level loss of rxlineclk signal one second in terrupt hdlc controller block transmit hdlc - start of trans mission receive hdlc - start of reception transmit hdlc - end of transmission receive hdlc - end of reception fcs error receipt of abort sequence receipt of idle sequence slip buffer block slip buffer full slip buffer empty slip buffer - slip alarm & error block receipt of cas multi-frame yello w alarm detection of loss of signal condition detection of line code violation change in receive loss of framer condition change in receive ais condition receipt of fas frame yellow alarm t1/e1 frame block change in cas multi-frame alignmen t change in national bits change in cas signaling bi ts change in fas frame alignment change in the "in fr ame" condition detection of "frame mimicking data" detection of sync (crc-4/crc-6) errors detection of framing bit errors
xrt86l30 139 single t1/e1/j1 framer/liu combo rev. 1.0.1 the next task for the mp/mc is to determine exactly what feature of functional section within the devi ce requested the interrupt. determine the framer(s) requesting the interrupt if the interrupting device turns out to be the fram er, then the mp/mc must determine which of the four framer channels requested the interrupt. hence, upon reach ing this state, one of the very first things that t he mp/mc must do within the user framer interrupt service ro utine, is to perform a read of each of the block in terrupt status registers within all of the framer channels that have been enabled for interrupt generation via their respective interrupt control registers. table 165 lists the address for the block interrupt status r egisters associated with each of the framer channels within the framer. the bit-format of each of these block interrupt sta tus registers is listed below. t able 165: a ddress of the b lock i nterrupt s tatus r egisters f ramer n umber a ddress of b lock i nterrupt s tatus r egister 0 0x0b02 1 0x1b02 2 0x2b02 3 0x3b02 4 0x4b02 5 0x5b02 6 0x6b02 7 0x7b02 t able 166: b lock i nterrupt s tatus r egister r egister 321 b lock i nterrupt s tatus r egister (bisr) h ex a ddress : 0 x 0b00 b it f unction t ype d efault d escription -o peration 7 sa6 ro 0 sa6 interrupt status 7-6 lbcode ro 0 loopback code interrupt 5 rxclklos rur 0 rxclk los interrupt status indicates if framer n has experienced a loss of rec overed clock interrupt since last read of this register. 0 = loss of recovered clock interrupt has not occur red since last read of this register 1 = loss of recovered clock interrupt has occurred since last read of this register.
xrt86l30 140 rev. 1.0.1 single t1/e1/j1 framer/liu combo for a given framer, the block interrupt status regi ster presents the "interrupt request" status of eac h "interrupt block" within the framer. the purpose of the "block interrupt status register" is to help t he mp/mc identify which "interrupt block(s) have requested t he interrupt. whichever bit(s) are asserted, in thi s register, identifies which block(s) have experienced an "inte rrupt generating" condition, as presented in table 166 . once the mp/mc has read this register, it can deter mine which "branch" within the interrupt service ro utine that it must follow; in order to properly service this i nterrupt. 4 onesec rur 0 one second interrupt status indicates if the xrt86l30 has experienced a one sec ond interrupt since the last read of this register. 0 = no outstanding one second interrupts awaiting s ervice 1 = outstanding one second interrupt awaits service 3 hdlc ro 0 hdlc block interrupt status indicates if the hdlc block has an interrupt reques t awaiting ser- vice. 0 = no outstanding interrupt requests awaiting serv ice 1 = hdlc block has an interrupt request awaiting se rvice. interrupt service routine should branch to and read data link status register (address xa,06). n ote : this bit-field will be reset to 0 after the micropr ocessor has performed a read to the data link status register. 2 slip ro 0 slip buffer block interrupt status indicates if the slip buffer block has any outstand ing interrupt requests awaiting service. 0 = no outstanding interrupts awaiting service 1 = slip buffer block has an interrupt awaiting ser vice. interrupt ser- vice routine should branch to and read slip buffer interrupt status register (address 0xxa,0x09. n ote : this bit-field will be reset to 0 after the micropr ocessor has performed a read of the slip buffer interrupt statu s register. 1 alarm ro 0 alarm & error block interrupt status indicates if the alarm & error block has any outsta nding interrupts that are awaiting service. 0 = no outstanding interrupts awaiting service 1 = alarm & error block has an interrupt awaiting s ervice. interrupt serstatus register (address xa,02) n ote : this bit-field will be reset to 0 after the micropr ocessor has performed a read of the alarm & error interrupt sta tus register. 0 t1/e1 frame ro 0 t1/e1 framer block interrupt status indicates if an t1/e1 frame status interrupt reques t is awaiting ser- vice. 0 = no t1/e1 frame status interrupt is pending 1 = t1/e1 framer status interrupt is awaiting servi ce. t able 166: b lock i nterrupt s tatus r egister r egister 321 b lock i nterrupt s tatus r egister (bisr) h ex a ddress : 0 x 0b00 b it f unction t ype d efault d escription -o peration
xrt86l30 141 single t1/e1/j1 framer/liu combo rev. 1.0.1 the framer ic further supports the "interrupt block " hierarchy by providing the "block interrupt enabl e register. the bit-format of this register is identi cal to that for the "block interrupt status registe r", and is presented below for the sake of completeness. the block interrupt enable register permits the use r to individually enable or disable the interrupt r equesting capability of each of the "interrupt blocks" within the framer. if a particular bit-field, within this register contains the value "0"; then the corresponding functional bl ock has been disabled from generating any interrupt requests. the procedures for configuring, enabling and servic ing interrupts for each of these hierarchical level s is discussed below. 3.6.1 configuring the interrupt system, at the frame r level the xrt86l30 framer ic permits the user to enable o r disable each of the four framers for interrupt generation. further, the chip permits the user to m ake the following configuration selection. 1. whether the "source-level" interrupt status bits ar e "reset-upon-read" or "write-to-clear". 2. whether or not an "activated interrupt" is automati cally cleared. 3.6.1.1 enabling/disabling the framer for interrupt generation each of the four framers of the xrt86l30 framer can be enabled or disabled for interrupt generation. t his selection is made by writing the appropriate 0 or 1 to bit 0 (intrup_en) of the "interrupt control register" corresponding to that framer, (see table 168 .) t able 167: b lock i nterrupt e nable r egister r egister 322 b lock i nterrupt e nable r egister (bier) h ex a ddress : 0 x 0b01 b it f unction t ype d efault d escription -o peration 7 sa6_enb r/w 0 sa6 interrupt enable 6 lbcode_enb r/w 0 loopback code interrupt enable 5 rxclkloss r/w 0 rxlineclk loss interrupt enable 0 = disables interrupt 1 = enables interrupt 4 onesec_enb r/w 0 one second interrupt enable 0 = disables interrupt 1 = enables interrupt 3 hdlc_enb r/w 0 hdlc block interrupt enable 0 = disables all hdlc block interrupts 1 = enables hdlc block (for interrupt generation) a t the block level 2 slip_enb r/w 0 slip buffer block interrupt enable 0 = disables all slip buffer block interrupts 1 = enables slip buffer block at the block level 1 alarm_enb r/w 0 alarm & error block interrupt enable 0 = disables all alarm & error block interrupts 1 = enables alarm & error block at the block level 0 t1/e1frame_enb r/w 0 t1/e1 frame block enable 0 = disables all frame block interrupts 1 = enables the frame block at the block level
xrt86l30 142 rev. 1.0.1 single t1/e1/j1 framer/liu combo setting this bit-field to "0" disables all interrup ts within the framer. setting this bit-field to "1" enables the framer for interrupt generation (at the framer leve l). n ote : it is important to note that setting this bit-field to "1" does not enable all of the interrupts withi n the framer. a given interrupt must also be enabled at the block and sou rce-level, before it is enabled for interrupt gener ation. 3.6.1.2 configuring the "interrupt status bits", wit hin a given framer to be "reset-upon-read" or "write-to-clear". the xrt86l30 source-level interrupt status register bits can be configured to be either "reset-upon-re ad" or "write-to-clear". if the user configures the int errupt status registers to be "reset-upon-read", th en when the mp/mc is reading the interrupt status register, the following will happen. 1. the contents of the source-level interrupt status r egister will automatically be reset to "0x00", foll owing the read operation. 2. the interrupt request output pin (int ) will automatically toggle false (or "high") upon reading the interrupt status register containing the last activated inter rupt status bit. if the user configures the interrupt status registe rs to be "write-to-clear", then when the mp/mc is r eading the interrupt status register, the following will happe n. 1. the contents of the source-level interrupt status r egister will not be cleared to "0x00", following th e read operation. the mp/mc will have to write 0x00 to the interrupt status register in order to reset the co ntents of the register to 0x00. 2. reading the interrupt status register, which contai ns the activated bit(s) will not cause the "interru pt request output" pin (int ) to toggle false. the interrupt request output pin will not toggle false until the mp/mc has written 0x00 into this register. (hence, the interrupt service routine must include this wri te operation). the interrupt status register (associated with a gi ven framer) can be configured to be either "reset-u pon- read" or "write-to-clear" by writing the appropriat e value into bit 2, within the interrupt control re gister as indicated in table 168 . writing a "0" into this bit-field configures the in terrupt status registers to be "reset-upon-read" (r ur). conversely, writing a "1" into this bit-field confi gures the interrupt status registers to be "write-t o-clear". 3.6.1.3 automatic reset of interrupt enable bits occasionally, the user's system (which includes the framer ic), may experience a fault condition, such that a "framer interrupt condition" will continuously exis t. if this particular interrupt has been enabled (w ithin the t able 168: i nterrupt c ontrol r egister r egister 26 i nterrupt c ontrol r egister (icr) h ex a ddress : 0 x 011a b it m od e f unction t ype d efault d escription -o peration 7-3 reserved - - reserved 2 int_wc_rur r/w 0 interrupt write-to-clear or reset-up on-read select configures interrupt status bits to either rur or w rite-to-clear 0=interrupt status bit rur 1=interrupt status bit write-to-clear 1 enbclr r/w 0 interrupt enable auto clear 0=interrupt enable bits are not cleared after statu s reading 1=interrupt enable bits are cleared after status re ading 0 intrup_enb r/w 0 interrupt enable for framer_n enables framer n for interrupt generation. 0 = disables corresponding framer block for interru pt generation 1 = enables corresponding framer block for interrup t generation
xrt86l30 143 single t1/e1/j1 framer/liu combo rev. 1.0.1 framer), then the framer will generate an interrupt request to the mp/mc. afterwards, the mp/mc will a ttempt to service this interrupt by reading the appropriat e block-level and source-level interrupt status reg ister. additionally, the local mp/mc will attempt to perfo rm some "system-related" tasks in order to try to r esolve these conditions causing the interrupt. after the l ocal mc/mp has attempted all of these things, the f ramer ic will negate the int output pin. however, because this system fault sti ll remains, the condition causing the framer to issue this interrupt also exists. consequ ently, the framer ic will generate another interrup t request, which forces the mp/mc to once again attempt to ser vice this interrupt. this phenomenon quickly result s in the local mp/mc being "tied up" in a continuous cycle o f executing this one interrupt service routine. con sequently, the mp/mc (along with portions of the overall syste m) now becomes non-functional. in order to prevent this phenomenon from ever occur ring, the framer ic can be configured to automatica lly reset the "interrupt enable" bits, following their activation. this feature can be implemented by writ ing the appropriate value to bit 1 of the "interrupt contro l register" as indicated in table 168 . writing a "1" to this bit-field configures the fram er to reset a given interrupt following activation. writing a "0" to this bit-field configures the framer to leave the i nterrupt enabled, following its activation.
xrt86l30 144 rev. 1.0.1 single t1/e1/j1 framer/liu combo 4.0 general description and interface the xrt86l30 supports multiple interfaces for vario us modes of operation. the purpose of this section is to present a general overview of the common interfaces and their connection diagrams. each mode will be described in full detail in later sections of the d atasheet. n ote : for a brief tutorial on framing formats, see append ix a in the back of the datasheet. 4.1 physical interface the line interface unit generates/receives standard return-to-zero (rz) signals to the line interface for t1/e1/ j1 twisted pair or e1 coaxial cable. the physical interface is optimized by placing the terminating i mpedance inside the liu. this allows one bill of materials for all modes of operation reducing the number of e xternal components necessary in system design. the transmi tter outputs only require one dc blocking capacitor of 0.68 m f and a 1:2 step-up transformer. the receive path inputs only require one bypass capacitor of 0.1 m f connected to the center tap (ct) of the transformer and a 1:1 transformer. the receive ct bypass capa citor is required for long haul applications, and recommende d for short haul applications. figure 7 shows the typical connection diagram for the liu transmitters . figure 8 shows a typical connection diagram for the liu receivers. f igure 7. liu t ransmit c onnection d iagram u sing i nternal t ermination f igure 8. liu r eceive c onnection d iagram u sing i nternal t ermination t tip t ring xrt86l30 liu 1:2 internal impedance line interface t1/e1/j1 c=0.68uf one bill of materials transmitter output r tip r ring xrt86l30 liu 1:1 internal impedance line interface t1/e1/j1 one bill of materials receiver input 0.1 m f
xrt86l30 145 single t1/e1/j1 framer/liu combo rev. 1.0.1 4.2 r 3 technology (relayless / reconfigurable / redundanc y) redundancy is used to introduce reliability and pro tection into network card design. the redundant ca rd in many cases is an exact replicate of the primary car d, such that when a failure occurs the network proc essor can automatically switch to the backup card. exar s r 3 technology has re-defined ds-1/e1/j1 physical interface design for 1:1 and 1+1 redundancy applica tions. without relays and one bill of materials, e xar offers multi-port, integrated framer/liu solutions to assist high density aggregate applications and f raming requirements with reliability. the following secti on can be used as a reference for implementing r 3 technology with exars world leading framer/liu combo. 4.2.1 line card redundancy telecommunication system design requires signal int egrity and reliability. when a t1/e1 primary line card has a failure, it must be swapped with a backup line ca rd while maintaining connectivity to a backplane wi thout losing data. system designers can achieve this by implementing common redundancy schemes with the xrt86l30 framer/liu. exar offers features that are tailored to redundancy applications while reducing the number of components and providing system designers with solid reference designs. 4.2.2 typical redundancy schemes 1:1 one backup card for every primary card (facilit y protection) 1+1 one backup card for every primary card (line pr otection) n+1 one backup card for n primary cards 4.2.3 1:1 and 1+1 redundancy without relays the 1:1 facility protection and 1+1 line protection have one backup card for every primary card. when using 1:1 or 1+1 redundancy, the backup card has its tran smitters tri-stated and its receivers in high imped ance. this eliminates the need for external relays and provide s one bill of materials for all interface modes of operation. for 1+1 line protection, the receiver inputs on the backup card have the ability to monitor the line f or bit errors while in high impedance. the transmit and receive sections of the physical interface are described se parately. 4.2.4 transmit interface with 1:1 and 1+1 redundancy the transmitters on the backup card should be tri-s tated. select the appropriate impedance for the de sired mode of operation, t1/e1/j1. a 0.68uf capacitor is used in series with ttip for blocking dc bias. se e figure 9 . for a simplified block diagram of the transmit se ction for a 1:1 and 1+1 redundancy. f igure 9. s implified b lock d iagram of the t ransmit i nterface for 1:1 and 1+1 r edundancy t1/e1 line backplane interface primary card backup card xrt86l30 tx tx 0.68uf 0.68uf internal impedence 1:2 1:2 xrt86l30 internal impedence
xrt86l30 146 rev. 1.0.1 single t1/e1/j1 framer/liu combo 4.2.5 receive interface with 1:1 and 1+1 redundancy the receivers on the backup card should be programm ed for "high" impedance. since there is no externa l resistor in the circuit, the receivers on the backu p card will not load down the line interface. this key design feature eliminates the need for relays and provides one bill of materials for all interface modes of o peration. select the impedance for the desired mode of operat ion, t1/e1/j1. to swap the primary card, set the b ackup card to internal impedance, then the primary card t o "high" impedance. see figure 10 . for a simplified block diagram of the receive section for a 1:1 redundancy scheme. f igure 10. s implified b lock d iagram of the r eceive i nterface for 1:1 and 1+1 r edundancy "high" impedence internal impedence backplane interface primary card backup card xrt86l30 rx t1/e1 line rx 1:1 1:1 xrt86l30
xrt86l30 147 single t1/e1/j1 framer/liu combo rev. 1.0.1 4.3 power failure protection for 1:1 or 1+1 line card redundancy in t1/e1 applic ations, power failure could cause a line card to ch ange the characteristics of the line impedance, causing a de gradation in system performance. the xrt86l30 was designed to ensure reliability during power failure s. the liu has patented high impedance circuits th at allow the receiver inputs and the transmitter outputs to be in "high" impedance when the liu experiences a p ower failure or when the liu is powered off. n ote : for power failure protection, a transformer must be used to couple to the line interface. see the tan -56 application note for more details. 4.4 overvoltage and overcurrent protection physical layer devices such as lius that interface to telecommunications lines are exposed to overvolt age transients posed by environmental threats. an over voltage transient is a pulse of energy concentrated over a small period of time, usually under a few milliseco nds. these pulses are random and exceed the operat ing conditions of cmos transceiver ics. electronic equ ipment connecting to data lines are susceptible to many forms of overvoltage transients such as lightning, ac power faults and electrostatic discharge (esd). there are three important standards when designing a tele communications system to withstand overvoltage transients. ul1950 and fcc part 68 telcordia (bellcore) gr-1089 itu-t k.20, k.21 and k.41 n ote : for a reference design and performance, see the tan-54 application note for more details. 4.5 non-intrusive monitoring in non-intrusive monitoring applications, the trans mitters are shut off by setting txon "low". the re ceivers must be actively receiving data without interfering with the line impedance. the xrt86l30s internal termination ensures that the line termination meets t1/e1 specifications for 75 w, 100 w or 120 w while monitoring the data stream. system integrity is ma intained by placing the non-intrusive receiver in " high" impedance, equivalent to that of a 1+1 redundancy a pplication. a simplified block diagram of non-intr usive monitoring is shown in figure 11 . f igure 11. s implified b lock d iagram of a n on -i ntrusive m onitoring a pplication line card transceiver non-intrusive receiver node xrt86l30 xrt86l30 data traffic
xrt86l30 148 rev. 1.0.1 single t1/e1/j1 framer/liu combo 4.6 t1/e1 serial pcm interface the most common mode is the standard serial pcm int erface. within this mode, only the serial data, se rial clock, frame pulse and multi-frame pulse are requir ed for both the transmit and receive paths. for th e transmit path, only txser is a dedicated input to the device . all other signals to the transmit path in figure 12 can be programmed as either input or output. for the rece ive path, only rxser and rxmsync are dedicated outp uts from the device. all other signals in the receive path in figure 13 can be programmed as either input or output. f igure 12. t ransmit t1/e1 s erial pcm i nterface f igure 13. r eceive t1/e1 s erial pcm i nterface f ts1 txser txserclk (bi-directional) txsync (bi-directional) txmsync (bi-directional) ts2 ts24 n : txmsync = 4 * (txsync) sf : txmsync = 12 * (txsync) t1dm : txmsync = 12 * (txsync) slc-96 : txmsync = 12 * (txsync) esf : txmsync = 24 * (txsync) ts1 txserclk (bi-directional) txsync (bi-directional) txmsync (bi-directional) ts2 ts32 txmsync = 16 * (txsync) txser t1 e1 f ts1 rxser rxsercl k (bi-directional) rxsync (bi-directional) rxcrcsync ts2 ts24 n : rxcrcsync = 4 * (rxsync) sf : rxcrcsync = 12 * (rxsync) t1dm : rxcrcsync = 12 * (rxsync) slc-96 : rxcrcsync = 12 * (rxsync) esf : rxcrcsync = 24 * (rxsync) ts1 rxsercl k (bi-directional) rxsync (bi-directional) rxcasync ts2 ts32 rxcasync = 16 * (rxsync) rxser t1 e1
xrt86l30 149 single t1/e1/j1 framer/liu combo rev. 1.0.1 4.7 t1/e1 fractional interface the individual time slots can be enabled/disabled t o carry fractional ds-0 data. the purpose of this interface is to enable one or more time slots in the pcm data (t xser) to be replaced with the fractional ds-0 paylo ad. if this mode is selected, the dedicated hardware pin t xchn1/t1fr is used to input the fractional ds-0 dat a within the time slots that are enabled. the dedica ted hardware pin rxchn1/r1fr is used to output the fractional ds-0 data within the time slots that are enabled. figure 14 is a simplified diagram of the fractional interface. f igure 14. t1 f ractional i nterface tsn - tsm txchn1/t1fr txserclk txsync txmsync f t1 fractional data pcm ts[0-(n-1)] pcm ts[(m+1)-23] txser
xrt86l30 150 rev. 1.0.1 single t1/e1/j1 framer/liu combo 4.8 t1/e1 time slot substitution and control the time slots within pcm data are reserved for car rying individual ds-0s. however, the framer block (transmit or receive paths) can substitute the payl oad with various code definitions. each time slot can be independently programmed to carry normal pcm data o r a variety of user codes. in e1 mode, the user ca n substitute the transmit time slots 0 and 16, althou gh signaling and frame sync cannot be maintained. the following options for time slot substitution are av ailable: unchanged invert all bits invert even bits invert odd bits programmable user code busy 0xff vacant 0xd5 busy ts, busy 00 a-law, m -law invert the msb bit invert all bits except the msb bit prbs d/e channel (or fractional input) f igure 15. t1/e1 t ime s lot s ubstitution and c ontrol f ts n - ts n+m substitution txser txserclk txsync txmsync pcm data pcm data
xrt86l30 151 single t1/e1/j1 framer/liu combo rev. 1.0.1 4.9 robbed bit signaling/cas signaling signaling is used to convey status information rela tive to the individual ds-0s. if a particular ds- 0 is on hook, off hook, etc. this information is carried within t he robbed bits in t1 (sf/esf/slc-96) or the sixteen th time slot in e1. on the transmit path, the signaling informa tion can be inserted through the pcm data, internal registers, or a dedicated external signaling bus by programmin g the appropriate registers. on the receive path, the signaling information is extracted (if enabled) to the internal registers and the external signaling b us in addition to being embedded within the pcm data. if the user wishes to substitute the abcd values, the substitu tion only occurs in the pcm data. once substituted, the internal registers and the external signaling bus will not be affected. figure 16 is a simplified block diagram showing the signalin g interface. figure 17 is a timing diagram showing how to insert the abcd values for e ach time slot in esf / cas. figure 18 is a timing diagram showing how to insert the ab values for sf / slc-96 or 4-code signaling in esf / cas. f igure 16. r obbed b it s ignaling / cas s ignaling f igure 17. esf / cas e xternal s ignaling b us rbs/cas signaling substitution pcm data tx liu tscr internal reg's rx liu signaling extraction pcm data rsar internal reg's transmit direction receive direction txser txchn0/ txsig rxser rxchn0/ rxsig physical interface txsync txmsync txserclk txchn0/txsig txser f d c b a ts 1 d c b a d c b a ts 2 ts 3
xrt86l30 152 rev. 1.0.1 single t1/e1/j1 framer/liu combo f igure 18. sf / slc-96 or 4- code s ignaling in esf / cas e xternal s ignaling b us txsync txmsync txserclk txchn0/txsig txser f b a ts 1 b a b a ts 2 ts 3
xrt86l30 153 single t1/e1/j1 framer/liu combo rev. 1.0.1 4.10 overhead interface the overhead interface provides an option for inser ting the datalink bits into the transmit pcm data o r extracting the datalink bits from the receive pcm d ata. by default, the datalink information is proce ssed to and from the pcm data directly. on the transmit path, the overhead clock is automatically provided as a c lock reference to externally time the datalink bits. th e user should provide data on the rising edge of th e txohclk so that the framer can sample the datalink bits on the falling edge. on the receive path, the datalin k bits are updated on the rising edge of the rxohclk output pi n. in t1 esf mode, a datalink bit occurs every oth er frame. therefore, the default overhead interface i s operating at 4kbps. in e1 mode, the datalink bit s are located in the first time slot of each non-fas fram e. figure 19 is a simplified block diagram of the overhead interface. figure 20 is a simplified diagram for the t1 external overhe ad datalink bus. figure 21 is a simplified diagram for the e1 external overhead dat alink bus. f igure 19. t1/e1 o verhead i nterface f igure 20. t1 e xternal o verhead d atalink b us datalink bits pcm data tx liu rx liu datalink bits pcm data transmit direction receive direction txser txoh rxser rxoh physical interface txohclk rxohclk txsync txohclk (4khz) txoh frame1 frame6 frame5 frame4 frame2 frame3 datalink bit datalink bit datalink bit
xrt86l30 154 rev. 1.0.1 single t1/e1/j1 framer/liu combo f igure 21. e1 o verhead e xternal d atalink b us 4.11 framer bypass mode the framer bypass mode allows the xrt86l30 to be us ed as a stand alone line interface unit. in this m ode, a few of the backplane interface signals multiplex into the digital input/output signals to and from t he liu block. figure 22 shows a simplified block diagram of the f ramer bypass mode. f igure 22. s implified b lock d iagram of the f ramer b ypass m ode txsync txohclk txoh non-fas frame fas frame si txser 1 a s a 4 s a 7 s a 8 s a 6 s a 5 s a 4 s a 7 s a 8 if s a 4, s a 7, and s a 8 are selected 2-frame slip buffer elastic store tx serial data in tx liu interface 2-frame slip buffer elastic store rx liu interface rx framer rx serial data out tx framer tclk=txserclk tpos=txser tneg=txsync rclk=rxserclk rpos=rxser rneg=rxsync
xrt86l30 155 single t1/e1/j1 framer/liu combo rev. 1.0.1 4.12 high-speed non-multiplexed interface the speed of transferring data through a back plane interface in a non-multiplexed manner typically op erates at 1.544mbps, 2.048mbps, 4.096mbps, or 8.192mbps. for 12.352mbps and 16.384mbps, see the high-speed multiplexed section. the t1/e1 carrier signal out to or in from the line interface is always 1.544mhz and 2.048mhz respectively. however, the back plane int erface may be synchronous to a higher speed clock . for t1, as shown in figure 23 , is mapped into an e1 frame. therefore, every fou rth time slot contains non- valid data. for e1, as shown in figure 24 , is simply synchronized to the higher 8.192mhz c lock signal supplied to the txmsync input pin. f igure 23. t1 h igh -s peed n on -m ultiplexed i nterface f igure 24. e1 h igh -s peed n on -m ultiplexed i nterface txser txmsync 2.048mhz txserclk (1.544mhz) txsync non-multiplexed high speed interface (2.048mhz/4.09 6mhz/8.192mhz) f don't care ts 1 ts 2 ts 3 ts 4 ts 5 don't care txser txmsync (8.192mhz) txserclk (2.048mhz) txsync non-multiplexed high speed interface (2.048mhz/4.09 6mhz/8.192mhz) ts 1 ts 2 ts 3
xrt86l30 156 rev. 1.0.1 single t1/e1/j1 framer/liu combo 4.13 high-speed multiplexed interface in addition to the non-multiplexed mode, the framer can interface through the backplane in a high-spee d multiplexed application, either through a bit-muxed or byte-muxed (in hmvip or h.100) manner. in this mode, the chip is divided into two multiplexed blocks, fo ur channels per block. for t1, the high speed mult iplexed modes are 12.352mbps (bit-muxed, txsync is high d uring the f-bit), 16.384mbps (bit-muxed, txsync is high during the f-bit), 16.384mbps (hmvip: byte-m uxed, txsync is high during the last 2-bits of th e previous frame and the first 2-bits of the current frame), or 16.384mbps (h.100: byte-muxed, txsync is high during the last bit of the previous frame and the f irst bit in the current frame). for e1 mode, the o nly mode that is not supported is the 12.352mbps. the only other difference is that the f-bit (for t1 mode) becomes the first bit of the e1 frame. figure 25 is a simplified block diagram of transmit bit-muxe d application. figure 26 is a simplified block diagram of receive bit-muxed appli cation. although the data is only applied to chann el 4 or channel 0, the txserclk is necessary for all channe ls so that the transmit line rate is always equal t o the t1/ e1 carrier rate. f igure 25. t ransmit h igh -s peed b it m ultiplexed b lock d iagram f igure 26. r eceive h igh -s peed b it m ultiplexed b lock d iagram txser0 txmsync0 (16.384mhz) txserclk0 (2.048mhz) txserclk1 (2.048mhz) txserclk2 (2.048mhz) txserclk3 (2.048mhz) ttip/tring0 ttip/tring1 ttip/tring2 ttip/tring3 0b0 0b0 1b0 1b0 2b0 2b0 3b0 3b0 0b1 0b1 1b1 1b1 2b1 2b1 3b1 3b1 0b2 0b2 1b2 1b2 2b2 2b2 3b2 3b2 0b0 0b1 0b2 1b0 1b1 1b2 2b0 2b1 2b2 3b0 3b1 3b2 dmux txsync0 bit interleaved multiplexed mode rxser0 rxserclk0 (16.384mhz) rxlineclk0 (2.048mhz) rxlineclk1 (2.048mhz) rxlineclk2 (2.048mhz) rxlineclk3 (2.048mhz) rtip/rring0 rtip/rring1 rtip/rring2 rtip/rring3 0b0 0 0 1b0 0 2b0 3b0 0 0b1 0 0 1b1 0 2b1 3b1 0 0b2 0 0 1b2 0 2b2 3b2 0 0b0 0b1 0b2 1b0 1b1 1b2 2b0 2b1 2b2 3b0 3b1 3b2 mux rxsync0 bit interleaved multiplexed mode rz data
xrt86l30 157 single t1/e1/j1 framer/liu combo rev. 1.0.1 5.0 loopback modes of operation 5.1 liu physical interface loopback diagnostics the xrt86l30 supports several loopback modes for di agnostic testing. the following section describes the local analog loopback, remote loopback, digital loo pback, and dual loopback modes. the liu physical interface loopback modes are independent from the f ramer loopback modes. therefore, it is possible to configure multiple loopback modes creating tremendo us flexibility within the looped diagnostic feature s. 5.1.1 local analog loopback with local analog loopback activated, the transmit output data at ttip/tring is internally looped back to the analog inputs at rtip/rring. external inputs at rt ip/rring are ignored while valid transmit output da ta continues to be sent to the line. a simplified blo ck diagram of local analog loopback is shown in figure 27 . f igure 27. s implified b lock d iagram of l ocal a nalog l oopback n ote : the transmit diagnostic features such as taos, nlc generation, and qrss take priority over the transmi t input data at tclk/tpos/tneg. 5.1.2 remote loopback with remote loopback activated, the receive input d ata at rtip/rring is internally looped back to the transmit output data at ttip/tring. the remote loopback inc ludes the receive ja (if enabled). the transmit in put data at tclk/tpos/tneg are ignored while valid rece ive output data continues to be sent to the system. a simplified block diagram of remote loopback is show n in figure 28 . f igure 28. s implified b lock d iagram of r emote l oopback encoder decoder timing control data and clock recovery ja ja tx taos nlc/prbs/qrss ttip tring rtip rring tclk tpos tneg rclk rpos rneg rx encoder decoder timing control data and clock recovery ja ja tx rx taos nlc/prbs/qrss ttip tring rtip rring tclk tpos tneg rclk rpos rneg
xrt86l30 158 rev. 1.0.1 single t1/e1/j1 framer/liu combo 5.1.3 digital loopback with digital loopback activated, the transmit input data at tclk/tpos/tneg is looped back to the recei ve output data at rclk/rpos/rneg. the digital loopbac k mode includes the transmit ja (if enabled). the receive input data at rtip/rring is ignored while v alid transmit output data continues to be sent to t he line. a simplified block diagram of digital loopback is sho wn in figure 29 . f igure 29. s implified b lock d iagram of d igital l oopback 5.1.4 dual loopback with dual loopback activated, the remote loopback i s combined with the digital loopback. a simplified block diagram of dual loopback is shown in figure 30 . f igure 30. s implified b lock d iagram of d ual l oopback 5.1.5 framer remote line loopback the framer remote line loopback is almost identical to the liu physical interface remote loopback. th e digital data enters the framer interface, however d oes not enter the framing blocks. the main differe nce between the remote loopback and the framer remote l ine loopback is that the receive digital data from the liu is allowed to pass through the liu decoder/enco der circuitry before returning to the line interfac e. a simplified block diagram of framer remote line loop back is shown in figure 31 . f igure 31. s implified b lock d iagram of the f ramer r emote l ine l oopback encoder decoder timing control data and clock recovery ja ja tx rx taos nlc/prbs/qrss ttip tring rtip rring tclk tpos tneg rclk rpos rneg encoder decoder timing control data and clock recovery ja ja tx rx taos nlc/prbs/qrss ttip tring rtip rring tclk tpos tneg rclk rpos rneg encoder decoder timing control data and clock recovery ja ja tx rx taos nlc/prbs/qrss ttip tring rtip rring framer tx framer rx
xrt86l30 159 single t1/e1/j1 framer/liu combo rev. 1.0.1 5.1.6 framer payload loopback with framer payload loopback activated, the raw dat a within the receive time slots are looped back to the transmit framer block where the data is re-framed a ccording to the transmit timing. a simplified bloc k diagram of framer payload loopback is shown in figure 32 . f igure 32. s implified b lock d iagram of the f ramer l ocal l oopback 5.1.7 framer local loopback with framer local loopback activated, the transmit pcm input data is looped back to the receive pcm ou tput data. the receive input data at rtip/rring is igno red while an all ones signal is transmitted out to the line interface. a simplified block diagram of framer re mote line loopback is shown in figure 33 . f igure 33. s implified b lock d iagram of the f ramer l ocal l oopback tx serial clock rx serial clock st-bus 2-frame slip buffer elastic store tx serial data in tx liu interface 2-frame slip buffer elastic store rx liu interface rx framer rx serial data out tx framer plb tx serial clock rx serial clock st-bus 2-frame slip buffer elastic store tx serial data in tx liu interface 2-frame slip buffer elastic store rx liu interface rx framer rx serial data out tx framer llb
xrt86l30 160 rev. 1.0.1 single t1/e1/j1 framer/liu combo 6.0 hdlc controllers and lapd messages the purpose of the hdlc controllers is to allow mes sages to be stored for transport in the outbound tr ansmit framer block or extracted from the receive framer b lock through the lapd interface. the framer has 3 independent hdlc controllers. each hdlc controller has two 96-byte buffers for transmit and two 96-by te buffers for receive. the buffers are used to inser t messages into the out going data stream for trans mit or to extract messages from the incoming data stream from the receive path. total, there are twelve 96-byte buffers per channel. this allows multiple hdlc mes sages to be transported to and from exars framing device. f igure 34. hdlc c ontrollers 6.1 programming sequence for sending less than 96-by te messages once the data link source and the type of message h as been chosen, the following programming sequence can be followed to send (in this example) a 15-bye lapd message. n ote : to send more than 96-bytes, the programming sequenc e is slightly modified, which is described in the n ext section. 1. read the transmit data link byte count register to determine which buffer is available. 2. enable txsot in the data link interrupt enable regi ster. 3. write 0x0f into the transmit byte count register (a ssuming buffer 0 was available). 4. write the 15-byte message contents into register 0x 0600 (automatically incremented). 5. enable the lapd transmission by writing to register 0x0113. 6. once txeot occurs, the message has been transmitted . 6.2 programming sequence for sending large messages 1. read the transmit data link byte count register to determine which buffer is available. 2. enable txsot in the data link interrupt enable regi ster. 3. write 0x60 into the transmit byte count register (a ssuming buffer 0 was available). 4. write the first 96-bytes into register 0x0600 (buff er 0, automatically incremented). 5. enable the lapd transmission by writing to register 0x0113. 6. wait for the txsot before writing the next 96-bytes . 7. re-initiate the txsot interrupt enable. 8. write 0xe0 into the transmit byte count register (b uffer 1). 9. write the next 96-bytes into 0x0700 (buffer 1, auto matically incremented). 10. enable the lapd transmission by writing to register 0x0113. 11. wait for the txsot before writing the next 96-bytes . 12. continue until the entire message is sent. buffer 0 buffer 1 transmit receive 96-bytes 96-bytes 96-bytes 96-bytes transmit receive 96-bytes 96-bytes 96-bytes 96-bytes transmit receive 96-bytes 96-bytes 96-bytes 96-bytes hdlc1 hdlc2 hdlc3 buffer 0 buffer 1 buffer 0 buffer 1 channel n
xrt86l30 161 single t1/e1/j1 framer/liu combo rev. 1.0.1 6.3 programming sequence for receiving lapd messages the xrt86l30 can extract data link information from incoming ds1 frames from either the datalink bits themselves or the d/e time slots within the pcm inp ut data. to extract a lapd message, the following programming sequence can be used as a reference. 1. enable rxeot in the data link interrupt enable regi ster. 2. wait for the rxeot interrupt to occur. 3. once rxeot occurs, read the receive data link byte count register to determine which buffer the data i s extracted to and how many bytes are contained withi n the message. 4. read the exact amount of bytes from the proper buff er. if buffer 0, read 0x0600. if buffer 1, read 0 x0700. these two registers are automatically incremented. 6.4 ss7 (signaling system number 7) for esf in ds1 o nly to support ss7 specifications while receiving lapd messages, exars framer will generate an interrupt (if ss7 is enabled) once the hdlc controllers have rece ived more than 276 bytes within two flag sequences (0x7e) of a lapd message. each hdlc controller sup ports ss7. for example: to enable ss7 for all hdlc controllers, registers 0x0b11 (lapd1), 0x0b19 (lapd 2), 0x0b29 (lapd3) must be set to 0x01.
xrt86l30 162 rev. 1.0.1 single t1/e1/j1 framer/liu combo 6.5 ds1/e1 datalink transmission using the hdlc cont rollers the transmit framer block can insert data link info rmation to outbound ds1/e1 frames. the data link information can be inserted from the following sour ces. transmit overhead input interface (txoh) transmit hdlc1 controller transmit serial input interface (txser) n ote : hdlc1 is the dedicated controller for transmission of lapd messages through the datalink bits. if the datalink bits are not used for lapd messages, then hdlc1 can be u sed through the d/e time slots as with hdlc2 and hd lc3. the transmit data link source select bits within th e transmit data link select register (tsdlsr) deter mine the source for the data link bits in esf, slc?96, o r t1dm for ds1 and crc multi frame for e1. each tr ansmit hdlc controller contains four major functional modu les. bit-oriented signaling processor lapd controller slc?96 data link controller automatic performance report (apr) generation 6.6 transmit bos (bit oriented signaling) processor the transmit bos processor handles transmission of bos messages through the data link channel. the processor can be set for a specific amount of repet itions a certain bos message will be transmitted, o r it may be placed in an infinite loop. the processor can a lso insert a bos idle flag sequence and/or an abort sequence to be transmitted on the data link channel . 6.6.1 description of bos bit-oriented signaling messages are a 16-bit patter n of which a 6-bit message is embedded as shown in the following table. where d5 is the msb and d0 is the lsb. the rightmo st "1" is transmitted first. bos is classified int o the following two groups. priority codeword message command and response information 6.6.2 priority codeword message a priority codeword message is preemptive and has t he highest priority among all data link information . a priority codeword indicates a condition that is aff ecting the quality of service and thus shall be tra nsmitted until the condition no longer exists. the duration of tr ansmission should not be less than one second. a p riority codeword may be interrupted by software for 100 mil liseconds to send maintenance commands with a minimum interval of one second between interruption s. yellow alarm (00000000 11111111) is the only pr iority message defined in industry standards. 6.6.3 command and response information command and response information is transmitted to perform various functions. the bos processor can send a command and response by transmitting a minim um of 10 repetitions of the appropriate codeword pattern. a command and response data transmission initiates action at the remote end, while the remot e end will respond by sending bit-oriented response messa ge to acknowledge the received commands. the activation and deactivation of line remote loop-bac k and local payload loop-back functions are of this type. bos m essage f ormat 0 d5 d4 d3 d2 d1 d0 0 1 1 1 1 1 1 1 1
xrt86l30 163 single t1/e1/j1 framer/liu combo rev. 1.0.1 6.7 transmit mos (message oriented signaling) proces sor the transmit lapd controller implements the message -oriented protocol based on itu recommendation q.921 link access procedures on the d-channel. it p rovides the following functions. zero stuffing t1/e1 transmitter interface transmit message buffer access frame check sequence generation idle flag insertion abort sequence generation two 96-byte buffers in shared memory are allocated for each lapd to reduce the frequency of microproce ssor interrupts and alleviate the response time requirem ent for a microprocessor to handle each interrupt. there are no restrictions on the length of the message. however the 96-byte buffer is deep enough to hold o ne entire lapd path or test signal identification message. 6.7.1 discussion of mos message-oriented signals sent by the transmit lapd controller are messages conforming to itu recommendation q.921 lapd protocol. there are two types of message-oriented signals. one is a period ic performance report generated by the source or sink t1/e1 terminals as defined by ansi t1.403. the oth er is a path or test signal identification message that m ay be optionally generated by a terminal or interme diate equipment on a t1/e1 circuit. the message structu res of the performance report and path or test sign al identification message are shown in figure 35 for format a and format b respectively. 6.7.2 periodic performance report f igure 35. lapd f rame s tructure
xrt86l30 164 rev. 1.0.1 single t1/e1/j1 framer/liu combo the ansi t1.403 standard requires that the status o f the transmission quality be reported in one-secon d intervals. the one-second timing may be derived fr om the ds1 signal or from a separate equally accura te (32ppm) source. the phase of the one-second perio ds does not depend on the time of occurrence of any error event. a total of four seconds of informatio n is transmitted so that recovery operations may be initiated in case an error corrupts a message. counts of events shall be accumulated in each contiguous one-second interval. at the end of each one-second interval, a modulo-4 counter shall be incremented, and the ap propriate performance bits shall be set in bytes 5 and 6 in f ormat a. these octets and the octets that carry th e performance bits of the preceding three one-second intervals form the periodic performance report. the periodic performance report is made up of 14 by tes of data. bytes 1 to 4, 13, and 14 are the mess age header and bytes 5 to 12 contain data regarding the four most-recent one-second intervals. the periodi c performance report message uses the sapi/tei value of 0x14. 6.7.3 transmission-error event occurrences of transmission-error events indicate t he quality of transmission. the occurrences that s hall be detected and reported are: crc error event: a crc-6 error event is the occurre nce of a received crc code that is not identical to the corresponding locally calculated code. severely errored framing event: a severely-errored- framing event is the occurrence of two or more fram ing- bit-pattern errors within a 3-ms period. contiguous 3-ms intervals shall be examined. the 3-ms period may coincide with the esf. the severely-errored-framing event, while similar in form to criteria for decla ring a terminal has lost framing, is only designed as a pe rformance indicator; existing terminal out-of-frame criteria will continue to serve as the basis for terminal al arms. frame-synchronization-bit error event: a frame-sync hronization-bit-error event is the occurrence of a received framing-bit-pattern not meeting the severe ly-errored-framing event criteria. line-code violation event: a line-code violation ev ent is a bipolar violation of the incoming data. a line-code violation event for an b8zs-coded signal is the occ urrence of a received excessive zeros (exz) or a bi polar violation that is not part of a zero-substitution c ode. controlled slip event: a controlled-slip event is a replication, or deletion, of a t1 frame by the rec eiving terminal. a controlled slip may occur when there is a difference between the timing of a synchronous receiving terminal and the received signal. 6.7.4 path and test signal identification message the path identification message is used to identify the path between the source terminal and the sink terminal. the test signal identification message is used by t est signal generating equipment. both identificati on messages are made up of 82 bytes of data. byte 1 t o 4, 81 and 82 are the message header and bytes 5 t o 80 contain six data elements. these messages use the sapi/tei value of 0x15 to differentiate themselves from the performance report message. 6.7.5 frame structure the message structure of message-oriented signal is shown in figure 35 . two format types are shown in the figure: format a for frames which are sending perfo rmance report message and format b for frames which containing a path or test signal identification mes sage. the following abbreviations are used: sapi: service access point identifier c/r: command or response ea: extended address tei: terminal endpoint identifier fcs: frame check sequence 6.7.6 flag sequence all frames shall start and end with the flag sequen ce consisting of one 0 bit followed by six contiguo us 1 bits and one 0 bit. the flag preceding the address field is defined as the opening flag. the flag following the frame check sequence (fcs) field is defined as the closin g flag. the closing flag may also serve as the open ing flag
xrt86l30 165 single t1/e1/j1 framer/liu combo rev. 1.0.1 of the next frame, in some applications. however, a ll receivers must be able to accommodate receipt of one or more consecutive flags. 6.7.7 address field the address field consists of two octets. a single octet address field is reserved for lapb operation in order to allow a single lapb data link connection to be mult iplexed along with lapd data link connections. 6.7.8 address field extension bit (ea) the address field range is extended by reserving bi t 1 of the address field octets to indicate the fin al octet of the address field. the presence of a 1 in bit 1 of an address field octet signals that it is the final octet of the address field. the double octet address field for l apd operation shall have bit 1 of the first octet s et to a 0 and bit 1 of the second octet set to 1. 6.7.9 command or response bit (c/r) the command or response bit identifies a frame as e ither a command or a response. the user side shall send commands with the c/r bit set to 0, and respon ses with the c/r bit set to 1. the network side sha ll do the opposite; that is, commands are sent with c/r bit s et to 1, and responses are sent with c/r bit set to 0. 6.7.10 service access point identifier (sapi) the service access point identifier identifies a po int at which data link layer services are preceded by a data link layer entity type to a layer 3 or management e ntity. consequently, the sapi specifies a data link layer entity type that should process a data link layer frame an d also a layer 3 or management entity, which is to receive information carried by the data link layer frame. t he sapi allows 64 service access points to be speci fied, where bit 3 of the address field octet containing t he sapi is the least significant binary digit and b it 8 is the most significant. sapi values are 0x14 and 0x15 for perf ormance report message and path or test signal identification message respectively. 6.7.11 terminal endpoint identifier (tei) the tei sub-field allows 128 values where bit 2 of the address field octet containing the tei is the l east significant binary digit and bit 8 is the most sign ificant binary digit. the tei sub-field bit patter n 111 1111 (=127) is defined as the group tei. the group tei is assi gned permanently to the broadcast data link connect ion associated with the addressed service access point (sap). tei values other than 127 are used for the point- to-point data link connections associated with the addressed sap. non-automatic tei values (0-63) are selected by the user, and their allocation is the r esponsibility of the user. the network automatical ly selects and allocates tei values (64-126). 6.7.12 control field the control field identifies the type of frame whic h will be either a command or response. the contro l field shall consist of one or two octets. three types of contr ol field formats are specified: 2-octet numbered in formation transfer (i format), 2-octet supervisory functions (s format), and single-octet unnumbered information transfers and control functions (u format). the control fiel d for t1/e1 message is categorized as a single-octe t unacknowledged information transfer having the valu e 0x03. 6.7.13 frame check sequence (fcs) field the source of either the performance report or an i dentification message shall generate the frame chec k sequence. the fcs field shall be a 16-bit sequence. it shall be the ones complement of the sum (modul o 2) of: the remainder of xk (x15 + x14 + x13 + x12 + x11 + x10 + x9 + x8 + x7 + x6 + x5 + x4 + x3 + x2 + x + 1 ) divided (modulo 2) by the generator polynomial x16 + x12 + x5 + 1, where k is the number of bits in th e frame existing between, but not including, the final bit of the opening flag and the first bit of the fcs, e xcluding bits inserted for transparency, and the remainder of the division (modulo 2) by the gen erator polynomial x16 + x12 + x5 + 1, of the produc t of x16 by the content of the frame existing between, b ut not including, the final bit of the opening flag and the first bit of the fcs, excluding bits inserted for t ransparency. as a typical implementation at the transmitter, the initial content of the register of the device comp uting the remainder of the division is preset to all 1s and i s then modified by division by the generator polyno mial on the
xrt86l30 166 rev. 1.0.1 single t1/e1/j1 framer/liu combo address, control and information fields; the ones c omplement of the resulting remainder is transmitted as the 16-bit fcs. as a typical implementation at the receiver, the in itial content of the register of the device computi ng the remainder is preset to all 1s. the final remainder, after multiplication by x16 and then division (mod ulo 2) by the generator polynomial x16 + x12 + x5 + 1 of the seri al incoming protected bits and the fcs, will be 0001110100001111 (x15 through x0, respectively) in the absence of transmission errors. 6.7.14 transparency (zero stuffing) a transmitting data link layer entity shall examine the frame content between the opening and closing flag sequences, (address, control, information and fcs f ield) and shall insert a 0 bit after all sequences of five contiguous 1 bits (including the last five bits of the fcs) to ensure that an idle flag or an abort se quence is not simulated within the frame. a receiving data l ink layer entity shall examine the frame contents b etween the opening and closing flag sequences and shall discar d any 0 bit which directly follows five contiguous 1 bits.
xrt86l30 167 single t1/e1/j1 framer/liu combo rev. 1.0.1 6.8 transmit slc?96 data link controller the slc?96 t1 format is invented by at&t and is use d between the digital switch and a slc?96 formatted remote terminal. the purpose of the slc?96 product is to provide standard telephone service or plain o ld telephone service (pots) in areas of high subscribe r density but back-haul the traffic over t1 facilit ies. to support the slc?96 formatted remote terminal equ ipment, which is likely in an underground location, the t1 framer must: indicate equipment failures of the equipment to mai ntenance personal indicate failures of the pots lines test the pots lines provide redundancy on the t1s the slc?96 framing format is a d4 super-frame (sf) format with specialized data link information bits. these data link information bits take the position of the super-frame alignment (fs) bit positions. these bi ts consist of the following. concentrator bits (c, bit position 1 to 11) first spoiler bits (fs, bit position 12 to 14) maintenance bits (m, bit position 15 to 17) alarm bits (a, bit position 18 to 19) protection line switch bits (s, bit position 20 to 23) second spoiler bit (ss, bit position 24) resynchronization pattern (000111000111) in slc?96 mode, a six 6-bit datalink message will g enerate a one 9-ms frame of the slc?96 message format. the format of the datalink message is give n in bellcore tr-tsy-000008. when slc?96 mode is enabled, the fs bit is replaced by the data link me ssage read from memory at the beginning of each d4 super- frame. the xrt86l30 allocates two 6-byte buffers to provide the slc?96 data link controller an alterna ting access mechanism for information transmission. the bit ordering and usage is shown in the following ta ble; and the lsb is sent first. note that these registe rs are memory-based storage and they need to be ini tialized. each register is read out of memory once every six sf super-frames. the memory holding these registers owns a shared memory structure that is used by mult iple devices. these include ds1 transmit module, d s1 receive module, transmit lapd controller, transmit slc?96 data link controller, bit-oriented signaling processor, receive lapd controller, receive slc?96 data link controller, receive bit-oriented signalin g processor and microprocessor interface module. transmit slc ? 96 message registers b yte 5 4 3 2 1 0 1 0 1 1 1 0 0 2 c1 1 1 1 0 0 3 c7 c6 c5 c4 c3 c2 4 1 0 c11 c10 c9 c8 5 a2 a1 m3 m2 m1 0 6 0 1 s4 s3 s2 s1
xrt86l30 168 rev. 1.0.1 single t1/e1/j1 framer/liu combo 6.9 d/e time slot transmit hdlc controller block v5. 1 or v5.2 interface v5.2 protocol specifies a provision for transmittin g simultaneous lapd messages. since only one messa ge can be sent through the datalink bits at one time, an alternative path for communication is offered wi thin the framer block. this alternative path is known as d or e channel which can be transmitted through one o r more of the ds-0 time slots. d channel is used primaril y for data link applications. e channel is used pr imarily for signaling for circuit switching with multiple acces s configurations. a range of time slots can be ded icated to hdlc1, while a different range of time slots can be dedicated to hdlc2 to support v5.2. in addition, hdlc3 can be used to transmit a third lapd message if des ired. the hdlc controllers are implemented in the same manner as the datalink described above with the exc eption of the data link source select bits. 6.10 automatic performance report (apr) the apr feature allows the system to transmit pmon status within a lapd framing format a at one second intervals or within a single shot report. the data octets 5 through 12 within the lapd frame are repl aced with the pmon status for the previous one second interva l. t able 169: f raming f ormat for pmon s tatus i nserted within lapd by i nitiating apr n ote : the right most bit (bit 1) is transmitted first for all fields except for the two bytes of the fcs tha t are transmitted left most bit (bit 8) first. 6.10.1 bit value interpretation g1 = 1 if number of crc error events is equal to 1 g2 = 1 if number of crc error events is greater tha n 1 or equal to 5 g3 = 1 if number of crc error events is greater tha n 5 or equal to 10 g4 = 1 if number of crc error events is greater tha n 10 or equal to 100 g5 = 1 if number of crc error events is greater tha n 100 or equal to 319 g6 = 1 if number of crc error events is equal to 32 0 se = 1 if a severely errored framing event occurs ( fe shall be 0) fe = 1 if a framing synchronization bit error event occurs (se shall be 0) lv = 1 if a line code violation event occurs sl = 1 if slip event within the slip buffer occurs lb = 1 if payload loopback is activated u1 = not used (default = 0) octet number 8 7 6 5 4 3 2 1 time (s) 12 cr ea=0 3 ea=1 4 5 g3 lv g4 u1 u2 g5 sl g6 t 0 6 fe se lb g1 r g2 nm ni 7 g3 lv g4 u1 u2 g5 sl g6 t 0 - 1 8 fe se lb g1 r g2 nm ni 9 g3 lv g4 u1 u2 g5 sl g6 t 0 - 2 10 fe se lb g1 r g2 nm ni 11 g3 lv g4 u1 u2 g5 sl g6 t 0 - 3 12 fe se lb g1 r g2 nm ni 13 14 15 flag = 01111110 sapi = 001110 tei = 0000000 control = 00000011 = unacknowledged frame fcs flag = 01111110 fcs
xrt86l30 169 single t1/e1/j1 framer/liu combo rev. 1.0.1 u2 = not used (default = 0) r = not used (default = 0) nmni = one second report module 4 count
xrt86l30 170 rev. 1.0.1 single t1/e1/j1 framer/liu combo 7.0 overhead interface block the xrt86l30 has the ability to extract or insert d s1 data link information from or into the following : facility data link (fdl) bits in esf framing format mode signaling framing (fs) bits in slc?96 and n framing format mode remote signaling (r) bits in t1dm framing format mo de the source and destination of these inserted and ex tracted data link bits would be from either the int ernal hdlc controller or the external device accessible t hrough ds1 overhead interface block. the operation of the transmit overhead input interface block and the receive overhead output interface block will be discussed separately. 7.1 ds1 transmit overhead input interface block 7.1.1 description of the ds1 transmit overhead input interface block the ds1 transmit overhead input interface block wil l allow an external device to be the provider of th e facility data link (fdl) bits in esf framing format mode, si gnaling framing (fs) bits in the slc96 and n framin g format mode and remote signaling (r) bit in t1dm fr aming format mode. this interface provides interfac e signals and required interface timing to shift in p roper data link information at proper time. the transmit overhead input interface for a given f ramer consists of two signals. txohclk_n: the transmit overhead input interface cl ock output signal txoh_n: the transmit overhead input interface input signal. the transmit overhead input interface clock output pin (txohclk_n) generates a rising clock edge for e ach data link bit position according to configuration o f the framer. the data link equipment interfaced to the transmit overhead input interface block should upda te the data link bits on the txoh_n line upon detec tion of the rising edge of txohclk_n. the transmit overhead input interface block will sample and latch the da ta link bits on the txoh_n line on the falling edge of txoh clk_n. the data link bits will be included and tran smitted via the outgoing ds1 frames. the figure below shows block diagram of the ds1 tra nsmit overhead input interface of xrt86l30. 7.1.2 configure the ds1 transmit overhead input inte rface module as source of the facility data link (fdl) bits in esf framing format mode the fdl bits in esf framing format mode can be inse rted from: ds1 transmit overhead input interface block ds1 transmit hdlc controller ds1 transmit serial input interface. f igure 36. b lock d iagram of the ds1 t ransmit o verhead i nput i nterface of the xrt86l30 transmit overhead input interface txoh_n txohclk_n to transmit framer block
xrt86l30 171 single t1/e1/j1 framer/liu combo rev. 1.0.1 the transmit data link source select bits of the tr ansmit data link select register (tdlsr) controls t he insertion of data link bits into the fdl bits in es f framing format mode. the table below shows config uration of the transmit data link source select bits of the tr ansmit data link select register (tdlsr). if the transmit data link source select bits of the transmit data link select register are set to 10, the transmit overhead input interface block becomes inp ut source of the fdl bits. the xrt86l30 allows the user to select bandwidth of the facility data link channel in esf framing form at mode. the fdl can be either a 4khz or 2khz data lin k channel. the transmit data link bandwidth select bits of the transmit data link select register (tdlsr) d etermine the bandwidth of fdl channel in esf framin g format mode. the table below shows configuration of the transmit data link bandwidth select bits of the transmit da ta link select register (tdlsr).) figure 37 below shows the timing diagram of the input and ou tput signals associated with the ds1 transmit overhead input interface module in esf framing form at mode. transmit data link select register (tdlsr) (address = 0x010ah) b it n umber b it n ame b it t ype b it d escription 1-0 transmit data link source select r/w 00 - the facility data link bits are inserted in to the framer through either the lapd controller or the slc?96 buffer. 01 - the facility data link bits are inserted into the framer through the transmit serial data input interface via the txser_ n pins. 10 - the facility data link bits are inserted into the framer through the transmit overhead input interface via the txoh_n pi ns. 11 - the facility data link bits are forced to one by the framer. transmit data link select register (tdlsr) (address = 0x010ah) b it n umber b it n ame b it t ype b it d escription 5-4 transmit data link bandwidth select r/w 00 - the facility data link is a 4khz channel. a ll available fdl bits (first bit of every other frame) are used as data link bit s. 01 - the facility data link is a 2khz channel. only the odd fdl bits (first bit of frame 1, 5, 9) are used as data link bits. 10 - the facility data link is a 2khz channel. only the even fdl bits (first bit of frame 3, 7, 11) are used as data link bits.
xrt86l30 172 rev. 1.0.1 single t1/e1/j1 framer/liu combo 7.1.3 configure the ds1 transmit overhead input inte rface module as source of the signaling framing (fs) bits in n or slc?96 framing format mod e the fs bits in slc?96 and n framing format mode can be inserted from: ds1 transmit overhead input interface block ds1 transmit hdlc controller ds1 transmit serial input interface. the transmit data link source select bits of the tr ansmit data link select register (tdlsr) controls t he insertion of data link bits into the fs bits in n o r slc?96 framing format mode. the table below shows configuration of the transmit data link source sele ct bits of the transmit data link select register ( tdlsr). if the transmit data link source select bits of the transmit data link select register are set to 10, the transmit overhead input interface block becomes inp ut source of the fs bits. f igure 37. ds1 t ransmit o verhead i nput i nterface t iming in esf f raming f ormat mode transmit data link select register (tdlsr) (address = 0x010ah) b it n umber b it n ame b it t ype b it d escription 1-0 transmit data link source select r/w 00 - the signaling framing bits are inserted int o the framer through either the lapd controller or the slc?96 buffer. 01 - the signaling framing bits are inserted into t he framer through the transmit serial data input interface via the txser_ n pins. 10 - the signaling framing bits are inserted into t he framer through the transmit overhead input interface via the txoh_n pi ns. 11 - the signaling framing bits are forced to one b y the framer.
xrt86l30 173 single t1/e1/j1 framer/liu combo rev. 1.0.1 figure 38 below shows the timing diagram of the input and ou tput signals associated with the ds1 transmit overhead input interface module in n or slc?96 fram ing format mode. 7.1.4 configure the ds1 transmit overhead input inte rface module as source of the remote signaling (r) bits in t1dm framing format mode the r bits in t1dm framing format mode can be inser ted from: ds1 transmit overhead input interface block ds1 transmit hdlc controller ds1 transmit serial input interface. the transmit data link source select bits of the tr ansmit data link select register (tdlsr) controls t he insertion of data link bits into the r bits in t1dm framing format mode. the table below shows configu ration of the transmit data link source select bits of the tr ansmit data link select register (tdlsr). if the transmit data link source select bits of the transmit data link select register are set to 10, the transmit overhead input interface block becomes inp ut source of the r bits. since r bit presents in ti meslot 24 of every t1dm frame, therefore, bandwidth of t1d m data link channel is 8khz. figure 39 below shows the timing diagram of the input and ou tput signals associated with the ds1 transmit overhead input interface module in t1dm framing for mat mode. 7.2 ds1 receive overhead output interface block f igure 38. ds1 t ransmit o verhead i nput t iming in n or slc?96 f raming f ormat m ode transmit data link select register (tdlsr) (addres s = 0x010ah) b it n umber b it n ame b it t ype b it d escription 1-0 transmit data link source select r/w 00 - the remote signaling bits are inserted into the framer through either the lapd controller or the slc?96 buffer. 01 - the remote signaling bits are inserted into th e framer through the transmit serial data input interface via the txser_ n pins. 10 - the remote signaling bits are inserted into th e framer through the transmit overhead input interface via the txoh_n pi ns. 11 - the remote signaling bits are forced to one by the framer. f igure 39. ds1 t ransmit o verhead i nput i nterface module in t1dm f raming f ormat mode
xrt86l30 174 rev. 1.0.1 single t1/e1/j1 framer/liu combo 7.2.1 description of the ds1 receive overhead output interface block the ds1 receive overhead output interface block all ows an external device to be the consumer of the facility data link (fdl) bits in esf framing format mode, signaling framing (fs) bits in the slc96 and n framing format mode and remote signaling (r) bit in t1dm framing format mode this interface provides interface signals and required interface timing to shift out proper data link information at proper ti me. the receive overhead output interface for a given f ramer consists of two signals. rxohclk_n: the receive overhead output interface cl ock output signal rxoh_n: the receive overhead output interface outpu t signal. the receive overhead output interface clock output pin (rxohclk_n) generates a rising clock edge for each data link bit position according to configurat ion of the framer. the data link bits extracted fro m the incoming t1 frames are outputted from the receive o verhead output interface output pin (rxoh_n) at the rising edge of rxohclk_n. the data link equipment s hould sample and latch the data link bits at the fa lling edge of rxohclk_n. the figure below shows block diagram of the receive overhead output interface of xrt86l30. 7.2.2 configure the ds1 receive overhead output inte rface module as destination of the facility data link (fdl) bits in esf framing format mode the fdl bits in esf framing format mode can be extr acted to: ds1 receive overhead output interface block ds1 receive hdlc controller ds1 receive serial output interface. the receive data link source select bits of the rec eive data link select register (rdlsr) controls the extraction of fdl bits in esf framing format mode. the table below shows configuration of the receive data link source select bits of the receive data link se lect register (rdlsr). f igure 40. b lock d iagram of the ds1 r eceive o verhead o utput i nterface of xrt86l30 receive data link select register (tdlsr) (address = 0x010ah) b it n umber b it n ame b it t ype b it d escription 1-0 receive data link destination select r/w 00 - the extracted facility data link bits are s tored in either the lapd con- troller or the slc?96 buffer. at the same time, the extracted facility data link bits are outputted from the framer through the receive serial data output interface via the rxser_n pins. 01 - the extracted facility data link bits are outp utted from the framer through the receive serial data output interface vi a the rxser_n pins. 10 - the extracted facility data link bits are outp utted from the framer through the receive overhead output interface via t he rxoh_n pins. at the same time, the extracted facility data link bit s are outputted from the framer through the receive serial data output inter face via the rxser_n pins. 11 - the facility data link bits are forced to one by the framer. receive overhead output interface rxoh_n rxohclk_n from receive framer block
xrt86l30 175 single t1/e1/j1 framer/liu combo rev. 1.0.1 if the receive data link source select bits of the receive data link select register are set to 10, th e receive overhead output interface block becomes output sour ce of the fdl bits. the xrt86l30 allows the user to select bandwidth of the facility data link channel in esf framing form at mode. the fdl can be either a 4khz or 2khz data lin k channel. the receive data link bandwidth select b its of the receive data link select register (rdlsr) de termine the bandwidth of fdl channel in esf framing format mode. the table below shows configuration of the receive data link bandwidth select bits of the receive data link select register (tdlsr). figure 41 below shows the timing diagram of the output and o utput signals associated with the ds1 receive overhead output interface module in esf framing for mat mode. 7.2.3 configure the ds1 receive overhead output inte rface module as destination of the signaling framing (fs) bits in n or slc?96 framing format mode the fs bits in slc?96 and n framing format mode can be extracted to: ds1 receive overhead output interface block ds1 receive hdlc controller ds1 receive serial output interface. receive data link select register (tdlsr) (address = 0x010ah) b it n umber b it n ame b it t ype b it d escription 5-4 receive data link bandwidth select r/w 00 - the facility data link is a 4khz channel. a ll available fdl bits (first bit of every other frame) are used as data link bit s. 01 - the facility data link is a 2khz channel. only the odd fdl bits (first bit of frame 1, 5, 9) are used as data link bits. 10 - the facility data link is a 2khz channel. only the even fdl bits (first bit of frame 3, 7, 11) are used as data link bits. f igure 41. ds1 r eceive o verhead o utput i nterface module in esf framing format mode rxohclk (2khz,even) rxoh (2khz,even) rxoh (4khz) rxohclk (2khz,odd) rxoh (2khz,odd) frame # rxsync rxohclk (4khz) 1 2 6 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20
xrt86l30 176 rev. 1.0.1 single t1/e1/j1 framer/liu combo the receive data link source select bits of the rec eive data link select register (rdlsr) controls the destination of fs bits in n or slc?96 framing forma t mode. the table below shows configuration of the receive data link source select bits of the receive data link select register (rdlsr). if the receive data link source select bits of the receive data link select register are set to 10, th e receive overhead output interface block outputs fs bits ext racted from the incoming t1 data stream. figure 42 below shows the timing diagram of the output signa ls associated with the ds1 receive overhead output interface module in n or slc?96 framing form at mode. 7.2.4 configure the ds1 receive overhead output inte rface module as destination of the remote signaling (r) bits in t1dm framing format mode the r bits in t1dm framing format mode can be extra cted to: ds1 receive overhead output interface block ds1 receive hdlc controller ds1 receive serial output interface. receive data link select register (tdlsr) (address = 0x010ah) b it n umber b it n ame b it t ype b it d escription 1-0 receive data link source select r/w 00 - the extracted facility data link bits are s tored in either the lapd con- troller or the slc?96 buffer. at the same time, the extracted facility data link bits are outputted from the framer through the receive serial data output interface via the rxser_n pins. 01 - the extracted facility data link bits are outp utted from the framer through the receive serial data output interface vi a the rxser_n pins. 10 - the extracted facility data link bits are outp utted from the framer through the receive overhead output interface via t he rxoh_n pins. at the same time, the extracted facility data link bit s are outputted from the framer through the receive serial data output inter face via the rxser_n pins. 11 - the facility data link bits are forced to one by the framer. f igure 42. ds1 r eceive o verhead o utput i nterface t iming in n or slc?96 f raming f ormat mode
xrt86l30 177 single t1/e1/j1 framer/liu combo rev. 1.0.1 the receive data link source select bits of the rec eive data link select register (rdlsr) controls the destination of r bits in t1dm framing format mode. the table below shows configuration of the receive data link source select bits of the receive data link se lect register (rdlsr). if the receive data link source select bits of the receive data link select register are set to 10, th e receive overhead output interface block outputs the r bits extracted from the incoming t1 data stream. since r bit presents in timeslot 24 of every t1dm frame, theref ore, bandwidth of t1dm data link channel is 8khz. figure 43 below shows the timing diagram of the output signa ls associated with the ds1 receive overhead output interface module in t1dm framing format mode . 7.3 e1 overhead interface block the xrt86l30 has the ability to extract or insert e 1 data link information from or into the e1 nationa l bit sequence. the source and destination of these inser ted and extracted data link bits would be from eith er the internal hdlc controller or the external device acc essible through e1 overhead interface block. the operation of the transmit overhead input interface block and the receive overhead output interface blo ck will be discussed separately. 7.4 e1 transmit overhead input interface block 7.4.1 description of the e1 transmit overhead input interface block receive data link select register (rdlsr) (address = 0x010ah) b it n umber b it n ame b it t ype b it d escription 1-0 receive data link source select r/w 00 - the extracted facility data link bits are s tored in either the lapd con- troller or the slc ? 96 buffer. at the same time, the extracted facility data link bits are outputted from the framer through the receive serial data output interface via the rxser_n pins. 01 - the extracted facility data link bits are outp utted from the framer through the receive serial data output interface vi a the rxser_n pins. 10 - the extracted facility data link bits are outp utted from the framer through the receive overhead output interface via t he rxoh_n pins. at the same time, the extracted facility data link bit s are outputted from the framer through the receive serial data output inter face via the rxser_n pins. 11 - the facility data link bits are forced to one by the framer. f igure 43. ds1 r eceive o verhead o utput i nterface t iming in t1dm f raming f ormat mode
xrt86l30 178 rev. 1.0.1 single t1/e1/j1 framer/liu combo the e1 transmit overhead input interface block will allow an external device to be the provider of the e1 national bit sequence. this interface provides inte rface signals and required interface timing to shif t in proper data link information at proper time. the transmit overhead input interface for a given f ramer consists of two signals. txohclk_n: the transmit overhead input interface cl ock output signal txoh_n: the transmit overhead input interface input signal. the transmit overhead input interface clock output pin (txohclk_n) generates a rising clock edge for e ach national bit that is configured to carry data link information according to setting of the framer. the data link equipment interfaced to the transmit overhead input interface should update the data link bits on the txoh_n line upon detection of the rising edge of txohclk_n . the transmit overhead input interface block will sample and latch the data link bits on the txoh_n line on the falling edge of txohclk_n. the data link bits w ill be included in and transmitted via the outgoing e1 fra mes. the figure below shows block diagram of the ds1 tra nsmit overhead input interface of xrt86l30. 7.4.2 configure the e1 transmit overhead input inter face module as source of the national bit sequence in e1 framing format mode the national bit sequence in e1 framing format mode can be inserted from: e1 transmit overhead input interface block e1 transmit hdlc controller e1 transmit serial input interface the purpose of the transmit overhead input interfac e is to permit data link equipment direct access to the sa4 through sa8 national bits that are to be transp orted via the outbound frames. the transmit data li nk source select [1:0] bits, within the synchronizatio n mux register (smr) determine source of the sa4 th rough sa8 national bits to be inserted into the outgoing e1 frames. the table below shows configuration of the transmit data link source select [1:0] bits of the synchron ization mux register (smr). f igure 44. b lock d iagram of the e1 t ransmit o verhead i nput i nterface of xrt86l30 synchronization mux register (smr) (address = 0x01 09h) b it n umber b it n ame b it t ype b it d escription 3-2 transmit data link source select [1:0] r/w 00 - the sa4 through sa8 national bits are inser ted into the framer through the transmit serial data input interface vi a the txser_n pins. 01 - the sa4 through sa8 national bits are inserted into the framer through the transmit lapd controller. 10 - the sa4 through sa8 national bits are inserted into the framer through the transmit overhead input interface via t he txoh_n pins. 11 - the sa4 through sa8 national bits are inserted into the framer through the transmit serial data input interface via the tx ser_n pins. transmit overhead input interface txoh_n txohclk_n to transmit framer block
xrt86l30 179 single t1/e1/j1 framer/liu combo rev. 1.0.1 if the transmit data link source select bits of the transmit data link select register are set to 10, the transmit overhead input interface block becomes inp ut source of the fdl bits. the xrt86l30 allows the user to decide on the follo wing: how many of the national bits will be used to carry the data link information bits which of these national bits will be used to carry the data link information bits. the transmit sa data link select bits of the transm it signaling and data link select register (tsdlsr) determine which ones of the national bits are confi gured as data link bits in e1 framing format mode. depending upon the configuration of the transmit si gnaling and data link select register, either of th e following cases may exists: none of the national bits are used to transport the data link information bits (that is, data link cha nnel of xrt86l30 is inactive). any combination of between 1 and all 5 of the natio nal bits can be selected to transport the data link information bits. the table below shows configuration of the transmit sa data link select bits of the transmit signaling and data link select register (tsdlsr). for every sa bit that is selected to carry data lin k information, the transmit overhead input interfac e will supply a clock pulse, via the txohclk_n output pin, such that: the data link equipment interfaced to the transmit overhead input interface should update the data on the txoh_n line upon detection of the rising edge of tx ohclk_n. the transmit overhead input interface will sample a nd latch the data on the txoh_n line on the falling edge of txohclk_n. transmit signaling and data link select register (t sdlsr) (address = 0x010ah) b it n umber b it n ame b it t ype b it d escription 7 transmit sa8 data link select r/w 0 - source of the sa8 nation bit is not from the data link interface. 1 - source the sa8 national bit from the data link interface. 6 transmit sa7 data link select r/w 0 - source of the sa7 nation bit is not from the data link interface. 1 - source the sa7 national bit from the data link interface. 5 transmit sa6 data link select r/w 0 - source of the sa6 nation bit is not from the data link interface. 1 - source the sa6 national bit from the data link interface. 4 transmit sa5 data link select r/w 0 - source of the sa5 nation bit is not from the data link interface. 1 - source the sa5 national bit from the data link interface. 3 transmit sa4 data link select r/w 0 - source of the sa4 nation bit is not from the data link interface. 1 - source the sa4 national bit from the data link interface.
xrt86l30 180 rev. 1.0.1 single t1/e1/j1 framer/liu combo figure 45 below shows the timing diagram of the input and ou tput signals associated with the e1 transmit overhead input interface module in e1 framing forma t mode. 7.5 e1 receive overhead interface 7.5.1 description of the e1 receive overhead output interface block the e1 receive overhead output interface block will allow an external device to be the consumer of the e1 national bit sequence. this interface provides inte rface signals and required interface timing to shif t out proper data link information at proper time. the receive overhead output interface for a given f ramer consists of two signals. rxohclk_n: the receive overhead output interface cl ock output signal rxoh_n: the receive overhead output interface outpu t signal. the receive overhead output interface clock output pin (rxohclk_n) generates a rising clock edge for each national bit that is configured to carry data link information according to setting of the framer . the data link bits extracted from the incoming e1 frames are outputted from the receive overhead output interfa ce output pin (rxoh_n) before the rising edge of rxohc lk_n. the data link equipment should sample and lat ch the data link bits at the rising edge of rxohclk_n. the figure below shows block diagram of the receive overhead output interface of xrt86l30. f igure 45. e1 t ransmit o verhead i nput i nterface t iming f igure 46. b lock d iagram of the e1 r eceive o verhead o utput i nterface of xrt86l30 receive overhead output interface rxoh_n rxohclk_n from receive framer block
xrt86l30 181 single t1/e1/j1 framer/liu combo rev. 1.0.1 7.5.2 configure the e1 receive overhead output inter face module as source of the national bit sequence in e1 framing format mode the national bit sequence in e1 framing format mode can be extracted and directed to: e1 receive overhead output interface block e1 receive hdlc controller e1 receive serial output interface the purpose of the receive overhead output interfac e is to permit data link equipment to have direct a ccess to the sa4 through sa8 national bits that are extra cted from the incoming e1 frames. independent of th e availability of the e1 receive hdlc controller modu le, the xrt86l30 always output the received nationa l bits through the receive overhead output interface block . the xrt86l30 allows the user to decide on the follo wing: how many of the national bits is used to carry the data link information bits which of these national bits is used to carry the d ata link information bits. the receive sa data link select bits of the receive signaling and data link select register (tsdlsr) determine which ones of the national bits are confi gured as data link bits in e1 framing format mode. depending upon the configuration of the receive sig naling and data link select register, either of the following cases may exists: none of the received national bits are used to tran sport the data link information bits (that is, data link channel of xrt86l30 is inactive). any combination of between 1 and all 5 of the recei ved national bits are used to transport the data li nk information bits. the table below shows configuration of the receive sa data link select bits of the receive signaling a nd data link select register (rsdlsr). for every received sa bit that is determined to car ry data link information, the receive overhead outp ut interface will supply a clock pulse, via the rxohcl k_n output pin, such that: the receive overhead output interface should update the data on the rxoh_n line before the rising edge of rxohclk_n. the external data link equipment interfaced to the receive overhead output interface will sample and l atch the data on the rxoh_n line on the rising edge of r xohclk_n. receive signaling and data link select register (rs dlsr) (address = 0x010ch) b it n umber b it n ame b it t ype b it d escription 7 receive sa8 data link select r/w 0 - the received sa8 nation bit is not extracted to the data link interface. 1 - the received sa8 nation bit is extracted to the data link interface. 6 receive sa7 data link select r/w 0 - the received sa7 nation bit is not extracted to the data link interface. 1 - the received sa7 nation bit is extracted to the data link interface. 5 receive sa6 data link select r/w 0 - the received sa6 nation bit is not extracted to the data link interface. 1 - the received sa6 nation bit is extracted to the data link interface. 4 receive sa5 data link select r/w 0 - the received sa5 nation bit is not extracted to the data link interface. 1 - the received sa5 nation bit is extracted to the data link interface. 3 receive sa4 data link select r/w 0 - the received sa4 nation bit is not extracted to the data link interface. 1 - the received sa4 nation bit is extracted to the data link interface.
xrt86l30 182 rev. 1.0.1 single t1/e1/j1 framer/liu combo figure 47 below shows the timing diagram of the output signa ls associated with the e1 receive overhead output interface module in e1 framing format mode. f igure 47. e1 r eceive o verhead o utput i nterface t iming
xrt86l30 183 single t1/e1/j1 framer/liu combo rev. 1.0.1 8.0 liu transmit path 8.1 transmit diagnostic features in addition to taos, the xrt86l30 offers multiple d iagnostic features for analyzing network integrity such as ataos, network loop code generation, and qrss on a per channel basis by programming the appropriate registers. these diagnostic features take priority over the digital data provided by the framer block . the transmitters will send the diagnostic code to the l ine and will be maintained in the digital loopback if selected. 8.1.1 taos (transmit all ones) the xrt86l30 has the ability to transmit all ones o n a per channel basis by programming the appropriat e channel register. this function takes priority ove r the digital data provided by the framer block. f or example: if a fixed "0011" pattern is provided by the framer block and taos is enabled, the transmitter will ou tput all ones. figure 48 is a diagram showing the all ones signal at ttip a nd tring. f igure 48. taos (t ransmit a ll o nes ) taos 1 1 1
xrt86l30 184 rev. 1.0.1 single t1/e1/j1 framer/liu combo 8.1.2 ataos (automatic transmit all ones) if ataos is selected by programming the appropriate global register, an ami all ones signal will be tr ansmitted for each channel that experiences an rlos condition . if rlos does not occur, the ataos will remain in active until an rlos on a given channel occurs. a simplif ied block diagram of the ataos function is shown in figure 49 . f igure 49. s implified b lock d iagram of the ataos f unction 8.1.3 network loop up code by setting the liu to generate a nluc, the transmit ters will send out a repeating "00001" pattern. th e output waveform is shown in figure 50 . f igure 50. n etwork l oop u p c ode g eneration 8.1.4 network loop down code by setting the liu to generate a nldc, the transmit ters will send out a repeating "001" pattern. the output waveform is shown in figure 51 . f igure 51. n etwork l oop d own c ode g eneration rlos ataos taos ttip tring tx network loop-up code 1 1 0 0 0 0 0 0 0 0 1 network loop-down code 1 1 1 1 0 0 0 0 0 0 0
xrt86l30 185 single t1/e1/j1 framer/liu combo rev. 1.0.1 8.1.5 qrss generation the xrt86l30 can transmit a qrss random sequence to a remote location from ttip/tring. the polynomial is shown in table 170 . 8.2 t1 long haul line build out (lbo) the long haul transmitter output pulses are generat ed using a 7-bit internal dac (6-bits plus the msb sign bit). the line build out can be set to -7.5db, -15db, or -22db cable attenuation by programming the appropri ate channel register. the long haul lbo consist of 32 discrete time segments extending over four consecut ive periods of tclk. as the lbo attenuation is increas ed, the pulse amplitude is reduced so that the wave form complies with ansi t1.403 specifications. a long h aul pulse with -7.5db attenuation is shown in figure 52 , a pulse with -15db attenuation is shown in figure 53 , and a pulse with -22.5db attenuation is shown in figure 54 . f igure 52. l ong h aul l ine b uild o ut with -7.5 d b a ttenuation f igure 53. l ong h aul l ine b uild o ut with -15 d b a ttenuation t able 170: r andom b it s equence p olynomials r andom p attern t1 e1 qrss/prbs 2 20 - 1 2 15 - 1
xrt86l30 186 rev. 1.0.1 single t1/e1/j1 framer/liu combo f igure 54. l ong h aul l ine b uild o ut with -22.5 d b a ttenuation 8.3 t1 short haul line build out (lbo) the short haul transmitter output pulses are genera ted using a 7-bit internal dac (6-bit plus the msb sign bit). the line build out can be set to interface to five different ranges of cable attenuation by programmin g the appropriate channel register. the pulse shape is d ivided into eight discrete time segments which are set to fixed values to comply with the pulse template. to program the eight segments individually to optimiz e a special line build out, see the arbitrary pulse sec tion of this datasheet. the short haul lbo setting s are shown in table 171 8.3.1 arbitrary pulse generator in t1 mode only, the arbitrary pulse generator divi des the pulse into eight individual segments. each segment is set by a 7-bit binary word by programming the ap propriate channel register. this allows the system designer to set the overshoot, amplitude, and under shoot for a unique line build out. the msb (bit 7) is a sign- bit. if the sign-bit is set to "0", the segment wi ll move in a positive direction relative to a flat line (zero) condition. if this sign-bit is set to "1", the seg ment will move in a negative direction relative to a flat line condition. the resolution of the dac is typically 60mv per lsb. thus, writing 7-bit = 1111111 will c lamp the output at either voltage rail corresponding to a ma ximum amplitude. a pulse with numbered segments is shown in figure 55 . t able 171: s hort h aul l ine b uild o ut lbo setting eqc[4:0] r ange of c able a ttenuation 08h (01000) 0 - 133 feet 09h (01001) 133 - 266 feet 0ah (01010) 266 - 399 feet 0bh (01011) 399 - 533 feet 0ch (01100) 533 - 655 feet
xrt86l30 187 single t1/e1/j1 framer/liu combo rev. 1.0.1 f igure 55. a rbitrary p ulse s egment a ssignment n ote : by default, the arbitrary segments are programmed t o 0x00h. the transmitter outputs will result in an all zero pattern to the line interface. 8.3.2 dmo (digital monitor output) the driver monitor circuit is used to detect transm it driver failures by monitoring the activities at ttip/tring outputs. driver failure may be caused by a short c ircuit in the primary transformer or system problem s at the transmit inputs. if the transmitter of a channel h as no output for more than 128 clock cycles, dmo go es "high" until a valid transmit pulse is detected. if the d mo interrupt is enabled, the change in status of dm o will cause the interrupt pin to go "low". once the status reg ister is read, the interrupt pin will return "high" and the status register will be reset (rur). 8.3.3 transmit jitter attenuator the transmit path has a dedicated jitter attenuator to reduce phase and frequency jitter in the transm it clock. the jitter attenuator uses a data fifo (first in fi rst out) with a programmable depth of 32-bit or 64- bit. when the read and write pointers of the fifo are within 2-bits of over-flowing or under-flowing, the bandwi dth of the jitter attenuator is widened to track the short ter m input jitter, thereby avoiding data corruption. when this condition occurs, the jitter attenuator will not at tenuate input jitter until the read/write pointers position is outside the 2-bit window. in t1 mode, the bandwidt h of the ja is always set to 3hz. in e1 mode, the bandwidth is programmable to either 10hz or 1.5hz ( 1.5hz automatically selects the 64-bit fifo depth). the ja has a clock delay equal to ? of the fifo bit dep th. n ote : the receive path has a dedicated jitter attenuator. see the receive path line interface section. 1 2 3 4 5 6 7 8 segment register 1 0x0f08 2 0x0f09 3 0x0f0a 4 0x0f0b 5 0x0f0c 6 0x0f0d 7 0x0f0e 8 0x0f0f
xrt86l30 188 rev. 1.0.1 single t1/e1/j1 framer/liu combo 8.4 line termination (ttip/tring) the output stage of the transmit path generates sta ndard return-to-zero (rz) signals to the line inter face for t1/ e1/j1 twisted pair or e1 coaxial cable. the physic al interface is optimized by placing the terminatin g impedance inside the liu. this allows one bill of materials for all modes of operation reducing the n umber of external components necessary in system design. th e transmitter outputs only require one dc blocking capacitor of 0.68 m f. for redundancy applications (or simply to tri-s tate the transmitters), set txtsel to a "1" in the appropriate channel register. a typical transm it interface is shown in figure 56 . f igure 56. t ypical c onnection d iagram u sing i nternal t ermination t tip t ring xrt86l30 liu 1:2 internal impedance line interface t1/e1/j1 c=0.68uf one bill of materials transmitter output
xrt86l30 189 single t1/e1/j1 framer/liu combo rev. 1.0.1 9.0 liu receive path 9.1 line termination (rtip/rring) 9.1.1 case 1: internal termination the input stage of the receive path accepts standar d t1/e1/j1 twisted pair or e1 coaxial cable inputs through rtip and rring. the physical interface is optimize d by placing the terminating impedance inside the l iu. this allows one bill of materials for all modes of operation reducing the number of external component s necessary in system design. the receive terminatio n impedance is selected by programming tersel[1:0] to match the line impedance. selecting the internal i mpedance is shown in table 172 . the xrt86l30 has the ability to switch the internal termination to "high" impedance by programming rxt sel in the appropriate channel register, if the rxtsel hardware pin is high. for internal termination, set rxtsel to "1". by default, rxtsel is set to "0" ("high" i mpedance). for redundancy applications, a dedicate d hardware pin (rxtsel) is available to control the r eceive termination for all channels simultaneously. this hardware pin is and-ed with the register bit. both , the register bit and the hardware pin must be set active for the receiver to be configured for internal impedanc e. figure 57 shows a typical connection diagram using the internal termination. f igure 57. t ypical c onnection d iagram u sing i nternal t ermination 9.1.2 case 2: internal termination with one external fixed resistor for all modes along with the internal termination, a high precisi on external fixed resistor can be used to optimize the return loss. this external resistor can be used for all m odes of operation ensuring one bill of materials. there are three resistor values that can be used by setting t he rxres[1:0] bits in the appropriate channel regis ter. selecting the value for the external fixed resistor is shown in table 173 . t able 172: s electing the i nternal i mpedance tersel[1:0] r eceive t ermination 0h (00) 100 w 1h (01) 110 w 2h (10) 75 w 3h (11) 120 w t able 173: s electing the v alue of the e xternal f ixed r esistor r x res[1:0] e xternal f ixed r esistor 0h (00) none 1h (01) 240 w 2h (10) 210 w 3h (11) 150 w r tip r ring xrt86l30 liu 1:1 internal impedance line interface t1/e1/j1 one bill of materials receiver input 0.1 m f
xrt86l30 190 rev. 1.0.1 single t1/e1/j1 framer/liu combo by default, rxres[1:0] is set to "none" for no exte rnal fixed resistor. if an external fixed resistor is used, the xrt86l30 uses the parallel combination of the exter nal fixed resistor and the internal termination as the input impedance. see figure 58 for a typical connection diagram using the externa l fixed resistor. n ote : without the external resistor, the xrt86l30 meets a ll return loss specifications. this mode was creat ed to add flexibility for optimizing return loss by using a h igh precision external resistor. f igure 58. t ypical c onnection d iagram u sing o ne e xternal f ixed r esistor 9.1.3 equalizer control the main objective of the equalizer is to amplify a n input attenuated signal to a pre-determined ampli tude that is acceptable to the peak detector circuit. using feedback from the peak detector, the equalizer will gain the input up to the maximum value specified by the equa lizer control bits, in the appropriate channel regi ster, normalizing the signal. once the signal has reache d the pre-determined amplitude, the signal is then processed within the peak detector and slicer circu it. a simplified block diagram of the equalizer an d peak detector is shown in figure 59 . f igure 59. s implified b lock d iagram of the e qualizer and p eak d etector 9.1.4 cable loss indicator the ability to monitor the cable loss attenuation o f the receiver inputs is a valuable feature. the x rt86l30 contains a per channel, read only register for cabl e loss indication. clos[5:0] is a 6-bit binary wor d that reports the value of cable loss in 1db steps with a n absolute accuracy of 1db. an example of -25db c able loss attenuation is shown in figure 60 . f igure 60. s implified b lock d iagram of the c able l oss i ndicator r tip r ring xrt86l30 liu 1:1 internal impedance line interface t1/e1/j1 r r=240 w , 210 w , or 150 w receiver input 0.1 m f peak detector & slicer rx equalizer rx equalizer control rtip rring -25db of cable loss equalizer and peak detector clos[5:0] = 0x19h (25dec = 19hex) -25db attenuated signal read only xrt86l30
xrt86l30 191 single t1/e1/j1 framer/liu combo rev. 1.0.1 9.2 receive sensitivity to meet long haul receive sensitivity requirements, the xrt86l30 can accept t1/e1/j1 signals that have been attenuated by 43db cable attenuation in e1 mod e or 36db cable attenuation in t1 mode without experiencing bit errors, lof, pattern synchronizati on, etc. short haul specifications are for 12db of flat loss in e1 mode. t1 specifications are 655 feet of cable l oss along with 6db of flat loss in t1 mode. the xr t86l30 can tolerate cable loss and flat loss beyond the in dustry specifications. the receive sensitivity in the short haul mode is approximately 4,000 feet without experienci ng bit errors, lof, pattern synchronization, etc. although data integrity is maintained, the rlos function (if enabled) will report an rlos condition according t o the receiver loss of signal section in this datasheet. the test configuration for measuring the receive s ensitivity is shown in figure 61 . f igure 61. t est c onfiguration for m easuring r eceive s ensitivity 9.2.1 ais (alarm indication signal) the xrt86l30 adheres to the itu-t g.775 specificati on for an all ones pattern. the alarm indication s ignal is set to "1" if an all ones pattern (at least 99.9% o nes density) is present for t, where t is 3ms to 75 ms in t1 mode. ais will clear when the ones density is not met within the same time period t. in e1 mode, the ais is set to "1" if the incoming signal has 2 or less zer os in a 512-bit window. ais will clear when the in coming signal has 3 or more zeros in the 512-bit window. 9.2.2 nlcd (network loop code detection) the network loop code detection can be programmed t o detect a loop-up, loop-down, or automatic loop code. if the network loop code detection is progra mmed for loop-up, the nlcd will be set "high" if a repeating pattern of "00001" occurs for more than 5 seconds. if the network loop code detection is programmed for loop-down, the nlcd will be set "hig h" if a repeating pattern of "001" occurs for more than 5 seconds. if the network loop code detection is pro grammed for automatic loop code, the liu is configu red to detect a loop-up code. if a loop-up code is detect ed for more than 5 seconds, the xrt86l30 will automatically program the channel into a remote loo pback mode. the liu will remain in remote loopback even if the loop-up code disappears. the channel will c ontinue in remote loop back until a loop-down code is detected for more than 5 seconds (or, if the automa tic loop code is disabled) and then automatically r eturn to normal operation with no loop back. the process of the automatic loop code detection is shown in figure 62 . network analyzer e1 = prbs 2 15 - 1 t1 = prbs 2 23 - 1 external loopback xrt86l30 1-channel framer/liu cable loss flat loss tx tx rx rx w&g ant20
xrt86l30 192 rev. 1.0.1 single t1/e1/j1 framer/liu combo f igure 62. p rocess b lock for a utomatic l oop c ode d etection 9.2.3 flsd (fifo limit status detection) the purpose of the fifo limit status is to indicate when the read and write fifo pointers are within a pre- determined range (over-flow or under-flow indicatio n). the flsd is set to "1" if the fifo read and wr ite pointers are within 3-bits. 9.2.4 receive jitter attenuator the receive path has a dedicated jitter attenuator to reduce phase and frequency jitter in the recover ed clock. the jitter attenuator uses a data fifo (first in fi rst out) with a programmable depth of 32-bit or 64- bit. if the liu is used for line synchronization (loop timing s ystems), the ja should be enabled in the receive pa th. when the read and write pointers of the fifo are within 2-bits of over-flowing or under-flowing, the bandwi dth of the jitter attenuator is widened to track the short ter m input jitter, thereby avoiding data corruption. when this condition occurs, the jitter attenuator will not at tenuate input jitter until the read/write pointers position is outside the 2-bit window. in t1 mode, the bandwidt h of the ja is always set to 3hz. in e1 mode, the bandwidth is programmable to either 10hz or 1.5hz ( 1.5hz automatically selects the 64-bit fifo depth). the ja has a clock delay equal to ? of the fifo bit dep th. n ote : the transmit path has a dedicated jitter attenuator . see the transmit path line interface section. 9.2.5 rxmute (receiver los with data muting) the receive muting function can be selected by sett ing rxmute to "1" in the appropriate global registe r. if selected, any channel that experiences an rlos cond ition will automatically pull the output of the liu section "low" to prevent data chattering. if rlos does not occur, the rxmute will remain inactive until an rl os on a given channel occurs. the default setting for rxmu te is "0" which is disabled. a simplified block di agram of the rxmute function is shown in figure 63 . automatic remote loopback loop-up code for 5 sec? yes no loop-down code for 5 sec? no yes disable remote loopback
xrt86l30 193 single t1/e1/j1 framer/liu combo rev. 1.0.1 f igure 63. s implified b lock d iagram of the r x mute f unction rlos rxmute digital output liu framer
xrt86l30 194 rev. 1.0.1 single t1/e1/j1 framer/liu combo 10.0 the e1 transmit/receive framer 10.1 description of the transmit/receive payload dat a input interface block each of the four framers within the xrt86l30 device includes a transmit and receive payload data input interface block. although most configurations are independent for the tx and rx path, once e1 framing has been selected, both the tx and rx must operate in e 1. the payload data input interface module (also k nown as the back-plane interface module) supports payloa d data to be taken from or presented to the system. in e1 mode, supported data rates are 2.048mbit/s, mvip 2. 048mbit/s, 4.096mbit/s, 8.192mbit/s, multiplexed 16.384mbit/s, hmvip 16.384mbit/s, or h.100 16.384mb it/s. 10.1.1 brief discussion of the transmit/receive payl oad data input interface block operating at xrt84v24 compatible 2.048mbit/s mode whether or not the transmit/receive interface signa ls have been chosen as inputs or outputs, the overa ll system timing diagrams remain the same. it is the responsibility of the terminal equipment to provide serial input data through the txser pin aligned with the t ransmit single-frame synchronization signal and the transmit multi-frame synchronization signal. figure 64 shows how to connect the transmit payload data input interface block to local terminal equipment. figure 65 shows how to connect the receive payload data output interface to local terminal equipment. f igure 64. i nterfacing the t ransmit p ath to local terminal equipment txserclk0 txser0 txmsync0 txsync0 txchclk0 txchn[4:0]_0 transmit payload data input interface chn 0 terminal equipment xrt86l30
xrt86l30 195 single t1/e1/j1 framer/liu combo rev. 1.0.1 figure 66 shows the waveforms for connecting the transmit pa yload data input interface block to local terminal equipment. figure 67 shows the waveforms for connecting the receive pay load data input interface block to local terminal equipment. f igure 65. i nterfacing the r eceive p ath to local terminal equipment f igure 66. w aveforms for connecting the t ransmit p ayload d ata i nput i nterface b lock to local t erminal e quipment rxserclk0 rxser0 rxmsync0 rxsync0 rxchclk0 rxchn[4:0]_0 receive payload data input interface chn 0 terminal equipment xrt86l30 c txserclk txserclk (inv) txser txsync(input) txchclk txchn[4:0] txchn[0]/txsig txchclk txchn[2]/txts txchn[1]/txfrtd c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 input data input data signaling input data timeslot #1 timeslot #15 timeslot #16 timeslot #32 timeslot 32 timeslot 1 timeslot 15 timeslot 16 a b d c a b d c a b d c a b d if tx fractional e1 input enable = 0 if tx fractional e1 input enable = 1
xrt86l30 196 rev. 1.0.1 single t1/e1/j1 framer/liu combo f igure 67. w aveforms for connecting the r eceive p ayload d ata i nput i nterface b lock to local t er - minal e quipment c rxserclk rxser rxsync(output) rxtsclk rxtsb[4:0] rxtsb[0]/rxsig rxtsclk rxtsb[2]/rxchn rxtsb[1]/rxfrtd c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 8 7 6 5 4 3 2 1 a b d c a b d c a b d c a b d input data input data timeslot 31 timeslot 0 timeslot 5 timeslot 6 timeslot #0 timeslot #5 timeslot #6 timeslot #31 rx fractional enable bit = 0 rx fractional enable bit = 1
xrt86l30 197 single t1/e1/j1 framer/liu combo rev. 1.0.1 10.2 transmit/receive high-speed back-plane interfac e the high-speed back-plane interface supports payloa d data to be taken from or presented to the termina l equipment at different data rates. in the non-mult iplexed mode, payload data of each channel are inte rfaced to the terminal equipment separately. each channel us es its own serial clock, serial data, single-frame synchronization signal and multi-frame synchronizat ion signals. 10.2.1 non-multiplexed high-speed mode when the back-plane interface data rate is mvip 2.0 48mbit/s, 4.096mbit/s and 8.192mbit/s, the interfac e signals are all configured as inputs, except the re ceive serial data on rxser and the multi frame sync pulse provided by the framer. the transmit serial clock for each channel is always an input clock with freq uency of 2.048 mhz for all data rates so that it may be used as the timing reference for the transmit line rate . the txmsync signal is configured as the transmit input clock with frequencies of 2.048 mhz, 4.096 mhz and 8.192 mhz respectively. it serves as the primary cl ock source for the high-speed back-plane interface. figure 68 shows how to connect the transmit non-multiplexed high-speed input interface block to local terminal equipment. figure 69 shows how to connect the receive non-multiplexed h igh-speed output interface to local terminal equipment. f igure 68. t ransmit n on -m ultiplexed h igh -s peed c onnection to local terminal equipment using mvip 2.048m bit / s , 4.096m bit / s , or 8.192m bit / s txserclk0 txser0 txmsync0 txsync0 transmit payload data input interface chn 0 terminal equipment xrt86l30 txmsync = 2.048/4.096/8.192mhz
xrt86l30 198 rev. 1.0.1 single t1/e1/j1 framer/liu combo figure 70 shows the waveforms for connecting the transmit no n-multiplexed high-speed input interface block to local terminal equipment. figure 71 shows the waveforms for connecting the receive non -multiplexed high-speed input interface block to local terminal equipment. f igure 69. r eceive n on -m ultiplexed h igh -s peed c onnection to local terminal equipment using mvip 2.048m bit / s , 4.096m bit / s , or 8.192m bit / s f igure 70. w aveforms for c onnecting the t ransmit n on -m ultiplexed h igh -s peed i nput i nterface at mvip 2.048m bit / s , 4.096m bit / s , and 8.192m bit / s rxserclk0 rxser0 rxmsync0 rxsync0 receive payload data input interface chn 0 terminal equipment xrt86l30 rxmsync = 2.048/4.096/8.192mhz txserclk txserclk (inv) txser txsync(input) txsync(input) mvip mode txchclk txchn[0]/txsig txsyncfrd=0 txchn[1]/txfrtd 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 c a b d don't care c a b d don't care c a b d don't care c a b d don't care don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 txchn[1]/txfrtd txchclk txsyncfrd=1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 c a b d don't care txmsync (2/4/8mhz)
xrt86l30 199 single t1/e1/j1 framer/liu combo rev. 1.0.1 f igure 71. w aveforms for c onnecting the r eceive n on -m ultiplexed h igh -s peed i nput i nterface at mvip 2.048m bit / s , 4.096m bit / s , and 8.192m bit / s rxserclk rxserclk (inv) rxser rxsync(input) rxsync(input) mvip mode rxchclk rxchn[0]/rxsig rxsyncfrd=0 rxchn[1]/rxfrtd 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 c a b d don't care c a b d don't care c a b d don't care c a b d don't care don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 rxchn[1]/rxfrtd rxchclk rxsyncfrd=1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 c a b d don't care timeslot 0 timeslot 1 timeslot 2 timeslot 3 timeslot 4 timeslot 5 rxserclk (2/4/8mhz)
xrt86l30 200 rev. 1.0.1 single t1/e1/j1 framer/liu combo 10.2.2 multiplexed high-speed mode when the back-plane interface data rate is 16.384mb it/s, hmvip 16.384mbit/s, and h.100 16.384mbit/s, t he interface signals are all configured as inputs, exc ept the receive serial data on rxser and the multi frame sync pulse provided by the framer. the transmit serial clock for each channel is always an input clock wit h frequency of 2.048 mhz for all data rates so that i t may be used as the timing reference for the trans mit line rate. the txmsync signal is configured as the tran smit input clock with frequency of 16.384 mhz. it s erves as the primary clock source for the high-speed back -plane interface. payload and signaling data of ch annel 0-3 are multiplexed onto the transmit serial data p in of channel 0. payload and signaling data of chan nel 4-7 are multiplexed onto the transmit serial data pin o f channel 4. the transmit single-frame synchronizat ion signal of channel 0 pulses high at the beginning of the multiplexed frame with data from channel 0-3 multiplexed together. the transmit single-frame syn chronization signal of channel 4 pulses high at the beginning of the multiplexed frame with data from c hannel 4-7 multiplexed together. it is the responsi bility of the terminal equipment to align the multiplexed tra nsmit serial data with the transmit single-frame synchronization pulse. additionally, each channel r equires the local terminal equipment to provide a f ree- running 2.048 mhz clock into the transmit serial cl ock input. the local terminal equipment maps four 2.048mbit/s e1 data streams into one 16.384mbit/s s erial data stream as described below: 1. payload data of four channels are repeated and grou ped together in a bit-interleaved way. the first pa y- load bit of timeslot 0 of channel 0 is sent first, followed by the first payload bit of timeslot 0 of channel 1 and 2. the first payload bit of timeslot 0 of chann el 3 is sent last. after the first bit of timeslot 0 of all four chann els are sent, it comes the second bit of timeslot 0 of channel 0 and so on. the table below demonstrates h ow payload bits of four channels are mapped into the 16.384mbit/s data stream. x y : the xth payload bit of channel y 2. the local terminal equipment also multiplexed signa ling bits with payload bits and sent them together through the 16.384mbit/s data stream. when the terminal equipment is sending the fifth pa yload bit of one channel, instead of sending it twi ce, it inserts the signaling bit a of that correspondin g channel. similarly, the sixth payload bit is foll owed by the signaling bit b of that corresponding channel; the seventh payload bit is followed by the signalin g bit c; the eighth payload bit is followed by the signal ing bit d. the following table illustrates how payload bits an d signaling bits are multiplexed together into the 16.384mbit/s data stream. first octet of 16.384mbit/s data stream b it 0 b it 1 b it 2 b it 3 b it 4 b it 5 b it 6 b it 7 1 0 1 0 1 1 1 1 1 2 1 2 1 3 1 3 second octet of 16.384mbit/s data stream b it 0 b it 1 b it 2 b it 3 b it 4 b it 5 b it 6 b it 7 2 0 2 0 2 1 2 1 2 2 2 2 2 3 2 3 fifth octet of 16.384mbit/s data stream b it 0 b it 1 b it 2 b it 3 b it 4 b it 5 b it 6 b it 7 5 0 a 0 5 1 a 1 5 2 a 2 5 3 a 3
xrt86l30 201 single t1/e1/j1 framer/liu combo rev. 1.0.1 x y : the xth payload bit of channel y a y : the signaling bit a of channel y 3. after the first octet of all four channels are sent , the local terminal equipment start sending the se cond octets following the same rules of step 1 and 2. the transmit single-frame synchronization signal of channel 0 pulses high for one clock cycle at the f irst bit position of the multiplexed data stream with data f rom channel 0-3 multiplexed together. the transmit single- frame synchronization signal of channel 4 pulses hi gh for one clock cycle at the first bit position of the data stream with data from channel 4-7 multiplexed toget her. by sampling the high pulse on the transmit sin gle- frame synchronization signal, the framer can positi on the beginning of the multiplexed e1 frame. it is the responsibility of the terminal equipment to align t he multiplexed transmit serial data with the transm it single- frame synchronization pulse. inside the framer, all the "don't care" bits will b e stripped away. the framing bits, signaling and pa yload data are de-multiplexed inside the xrt86l30 device and send to each individual channel. these data will be proc essed by each individual framer and send to liu interface . the local terminal equipment provides a free-runn ing 2.048mhz clock to the transmit serial input clock o f each channel. the framer will use this clock to c arry the processed payload and signaling data to the transmi t section of the device. figure 72 shows how to connect the transmit multiplexed high-speed input interface block to local terminal equipment. figure 73 shows how to connect the receive multiplexed high-speed outpu t interface to local terminal equipment. sixth octet of 16.384mbit/s data stream b it 0 b it 1 b it 2 b it 3 b it 4 b it 5 b it 6 b it 7 6 0 b 0 6 1 b 1 6 2 b 2 6 3 b 3 seventh octet of 16.384mbit/s data stream b it 0 b it 1 b it 2 b it 3 b it 4 b it 5 b it 6 b it 7 7 0 c 0 7 1 c 1 7 2 c 2 7 3 c 3 eighth octet of 16.384mbit/s data stream b it 0 b it 1 b it 2 b it 3 b it 4 b it 5 b it 6 b it 7 8 0 d 0 8 1 d 1 8 2 d 2 8 3 d 3
xrt86l30 202 rev. 1.0.1 single t1/e1/j1 framer/liu combo f igure 72. i nterfacing xrt86l30 t ransmit to local terminal equipment using 16.384m bit / s , hmvip 16.384m bit / s , and h.100 16.384m bit / s txser0 txmsync0 (16.384mhz) txsync0 txserclk0 (2.048mhz) transmit payload data input interface chn 0 terminal equipment xrt86l30
xrt86l30 203 single t1/e1/j1 framer/liu combo rev. 1.0.1 figure 74 shows the waveforms for connecting the transmit mu ltiplexed high-speed input interface block to local terminal equipment. figure 75 shows the waveforms for connecting the receive mul tiplexed high- speed input interface block to local terminal equip ment for hmvip. figure 76 shows the waveforms for f igure 73. i nterfacing xrt86l30 r eceive to local terminal equipment using 16.384m bit / s , hmvip 16.384m bit / s , and h.100 16.384m bit / s rxser0 rxserclk0 (16.384mhz) rxsync0 rxlineclk0 (2.048mhz) transmit payload data input interface chn 0 terminal equipment xrt86l30
xrt86l30 204 rev. 1.0.1 single t1/e1/j1 framer/liu combo connecting the receive multiplexed high-speed input interface block to local terminal equipment for hmvi.100p. f igure 74. w aveforms for c onnecting the t ransmit m ultiplexed h igh -s peed i nput i nterface at hmvip a nd h.100 16.384m bit / s mode f igure 75. w aveforms for c onnecting the r eceive m ultiplexed h igh -s peed i nput i nterface at hmvip 16.384m bit / s mode txinclk (16.384mhz) txinclk (inv) txser 1 2 1 2 5 2 5 2 1 0 1 0 2 0 2 0 3 0 4 0 3 0 4 0 5 0 5 0 6 0 6 0 7 3 7 3 8 3 8 3 h 0 h 0 h 0 h 0 h 0 h 0 h 0 h 0 56 cycles 5 3 5 3 6 3 6 3 7 3 7 3 8 3 8 3 0 0 a 2 a 2 0 0 0 0 0 a 0 0 a 0 b 0 b 0 c 3 c 3 d 3 d 3 1 1 1 1 1 1 1 1 56 cycles a 3 a 3 b 3 b 3 c 3 c 3 d 3 d 3 txsig txsync(input) hmvip, negative sync txsync(input) hmvip, positive sync start of frame x y : x is the bit number and y is the channel number txsync(input) h.100, negative sync txsync(input) h.100, positive sync delayer h.100 txsync(input) h.100, negative sync txsync(input) h.100, positive sync 0 0 rxserclk (16.384mhz) rxserclk (inv) rxser 1 2 1 2 5 2 5 2 1 0 1 0 2 0 2 0 3 0 4 0 3 0 4 0 5 0 5 0 6 0 6 0 7 3 7 3 8 3 8 3 h 0 h 1 h 0 h 1 h 2 h 2 h 3 h 3 56 cycles 5 3 5 3 6 3 6 3 7 3 7 3 8 3 8 3 0 0 a 2 a 2 0 0 0 0 0 0 0 0 a 0 a 0 b 0 b 0 c 3 c 3 d 3 d 3 1 1 1 1 1 1 1 1 56 cycles a 3 a 3 b 3 b 3 c 3 c 3 d 3 d 3 rxsig rxsync(input) hmvip, negative sync rxsync(input) hmvip, positive sync start of frame x y : x is the bit number and y is the channel number
xrt86l30 205 single t1/e1/j1 framer/liu combo rev. 1.0.1 f igure 76. w aveforms for c onnecting the r eceive m ultiplexed h igh -s peed i nput i nterface at h.100 16.384m bit / s mode rxserclk (16.384mhz) rxserclk (inv) rxser 1 2 1 2 5 2 5 2 1 0 1 0 2 0 2 0 3 0 4 0 3 0 4 0 5 0 5 0 6 0 6 0 7 3 7 3 8 3 8 3 h 0 h 1 h 0 h 1 h 2 h 2 h 3 h 3 56 cycles 5 3 5 3 6 3 6 3 7 3 7 3 8 3 8 3 0 0 a 2 a 2 0 0 0 0 0 0 0 0 a 0 a 0 b 0 b 0 c 3 c 3 d 3 d 3 1 1 1 1 1 1 1 1 56 cycles a 3 a 3 b 3 b 3 c 3 c 3 d 3 d 3 rxsig start of frame x y : x is the bit number and y is the channel number rxsync(input) h.100, negative sync rxsync(input) h.100, positive sync delayer h.100 rxsync(input) h.100, negative sync rxsync(input) h.100, positive sync
xrt86l30 206 rev. 1.0.1 single t1/e1/j1 framer/liu combo 10.3 brief discussion of common channel signaling in e1 framing format as the name referred, common channel signaling is s ignaling information common to all thirty voice or data channels of an e1 trunk. time slot 16 may be used t o carry common channel signaling data of up to a ra te of 64kbits/s. the national bits of time slot 0 may als o be used for common channel signaling. since there are five national bits of time slot 0 per every two e1 frames, the total bandwidth of the national bits is 20kbits/s. the common channel signaling is essentially data link i nformation that provides performance monitoring and a transmission quality report. 10.4 brief discussion of channel associated signalin g in e1 framing format signaling is required when dealing with voice and d ial-up data services in e1 applications. traditiona lly, signaling is provided on a dial-up telephone line a cross the talk-path. signaling is used to tell the receiver where the call or route is destined. the signal is sent through switches along the route to a distant end. common types of signals are: on hook off hook dial tone dialed digits ringing cycle busy tone a signal is consists of four bits namely a, b, c an d d. these bits define the state of the call for a particular time slot. time slot 16 of each e1 frame can carry cas s ignals for two e1 voice or data channels. therefor e, sixteen e1 frames are needed to carry cas signals f or all 32 e1 channels. the sixteen e1 frames then forms a cas multi-frame. 10.5 insert/extract signaling bits from tscr registe r the four most significant bits of the transmit sign aling control register (tscr) of each time slot can be used to store outgoing signaling data. the user can prog ram these bits through microprocessor access. if th e xrt86l30 framer is configure to insert signaling bi ts from tscr registers, the e1 transmit framer bloc k will fill up the time slot 16 octet with the signaling b its stored inside the tscr registers. the insertion of signaling bit into pcm data is done on a per-channel basis. t he most significant bit (bit 7) of tscr register is used to store signaling bit a. bit 6 is used to hold signal ing bit b. bit 5 is used to hold signaling bit c. b it 4 is used to hold signaling bit d. 10.6 insert/extract signaling bits from txchn[0]_n/t xsig pin the xrt86l30 framer can be configured to insert/ext ract signaling bits provided by external equipment through the external signaling bus. when the fract ional e1 mode is enabled, this bus is configured as txsig and rxsig. these pins act as an the signaling bus for the outbound e1 frames. figure 77 shows a timing diagram of the txsig input pin. figure 78 shows a timing diagram of the rxsig output pin. please note that the signaling bit a o f a certain channel coincides with bit 5 of the pcm data of that channel; signaling bit b coincides with bit 6 of th e pcm data; signaling bit c coincides with bit 7 of the pcm data and signaling bit d coincides with bit 8 (lsb) of the pcm data. f igure 77. t iming d iagram of the t x sig i nput
xrt86l30 207 single t1/e1/j1 framer/liu combo rev. 1.0.1 10.7 enable channel associated signaling and signali ng data source control the transmit signaling control register (tscr) of e ach channel selects source of signaling data to be inserted into the outgoing e1 frame and enables cha nnel associated signaling. as we mentioned before, the signaling data can be inserted from transmit signal ing control registers (tscr) of each timeslot, from the txsig_n input pin, from the txoh_n input pin or fro m the txser_n input pin. the transmit signaling dat a source select [1:0] bits of the transmit signaling control register (tscr) determines from which sourc es the signaling data is inserted from. f igure 78. t iming d iagram of the r x sig o utput
xrt86l30 208 rev. 1.0.1 single t1/e1/j1 framer/liu combo 11.0 the ds1 transmit/receive framer 11.1 description of the transmit/receive payload dat a input interface block each of the four framers within the xrt86l30 device includes a transmit and receive payload data input interface block. although most configurations are independent for the tx and rx path, once t1 framing has been selected, both the tx and rx must operate in t 1. the payload data input interface module (also k nown as the back-plane interface module) supports payloa d data to be taken from or presented to the system. in t1 modes, supported data rates are 1.544mbit/s, mvip 2 .048mbit/s, 4.096mbit/s, 8.192mbit/s, multiplexed 12.352mbit/s, 16.384mbit/s, hmvip 16.384mbit/s, or h.100 16.384mbit/s. 11.1.1 brief discussion of the transmit/receive payl oad data input interface block operating at 1.544mbit/s mode whether or not the transmit/receive interface signa ls have been chosen as inputs or outputs, the overa ll system timing diagrams remain the same. it is the responsibility of the terminal equipment to provide serial input data through the txser pin aligned with the t ransmit single-frame synchronization signal and the transmit multi-frame synchronization signal. figure 79 shows how to connect the transmit payload data input interface block to local terminal equipment. figure 80 shows how to connect the receive payload data output interface to local terminal equipment. f igure 79. i nterfacing the t ransmit p ath to local terminal equipment txserclk0 txser0 txmsync0 txsync0 txchclk0 txchn[4:0]_0 transmit payload data input interface chn 0 terminal equipment xrt86l30
xrt86l30 209 single t1/e1/j1 framer/liu combo rev. 1.0.1 figure 81 shows the waveforms for connecting the transmit pa yload data input interface block to local terminal equipment. figure 82 shows the waveforms for connecting the receive pay load data input interface block to local terminal equipment. f igure 80. i nterfacing the r eceive p ath to local terminal equipment f igure 81. w aveforms for connecting the t ransmit p ayload d ata i nput i nterface b lock to local t erminal e quipment rxserclk0 rxser0 rxmsync0 rxsync0 rxchclk0 rxchn[4:0]_0 receive payload data input interface chn 0 terminal equipment xrt86l30 c txserclk (1.544mhz) txserclk (inv) txser txsync(input) txtsclk txtsb[4:0] txtsb[0]/txsig txtsb[4:0] txtsb[2]/txts txtsb[1]/txfrtd f f c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 input data input data input data input data timeslot #0 timeslot #5 timeslot #6 timeslot #23 timeslot 23 timeslot 0 timeslot 5 timeslot 6 a b d c a b d c a b d c a b d if tx fractional input enbale = 0 if tx fractional input enbale = 1
xrt86l30 210 rev. 1.0.1 single t1/e1/j1 framer/liu combo f igure 82. w aveforms for connecting the r eceive p ayload d ata i nput i nterface b lock to local t er - minal e quipment c rxserclk rxser rxsync(output) rxtsclk rxtsb[4:0] rxtsb[0]/rxsig rxtsclk rxtsb[2]/rxts rxtsb[1]/rxfrtd c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 c1 c2 c3 c4 c5 8 7 6 5 4 3 2 1 a b d c a b d c a b d c a b d input data input data timeslot 23 timeslot 0 timeslot 5 timeslot 6 timeslot #0 timeslot #5 timeslot #6 timeslot #23 rx fractional enable bit = 0 rx fractional enable bit = 1 f
xrt86l30 211 single t1/e1/j1 framer/liu combo rev. 1.0.1 11.2 transmit/receive high-speed back-plane interfac e the high-speed back-plane interface supports payloa d data to be taken from or presented to the termina l equipment at different data rates. in the non-mult iplexed mode, payload data of each channel are inte rfaced to the terminal equipment separately. each channel us es its own serial clock, serial data, single-frame synchronization signal and multi-frame synchronizat ion signals. 11.2.1 t1 transmit/receive interface - mvip 2.048 mh z the back-plane interface is processing data at an e 1 equivalent data rate of 2.048mbit/s. the local t erminal equipment should pump in data grouped in 256-bit fr ame 8000 times every second. each frame consists o f thirty-two octets as in e1. the local terminal equ ipment maps a 193-bit t1 frame into this 256-bit fo rmat as described below: 1. the framing (f-bit) is mapped into msb of the first e1 time-slot. the local terminal equipment will st uff the other seven bits of the first octet with don't care bits that would be ignored by the framer. 2. payload data of t1 time-slot 0, 1 and 2 are mapped into e1 time-slot 1, 2 and 3. 3. the local terminal equipment will stuff e1 time-slo t 4 with eight don't care bits that would be ignore d by the framer. 4. following the same rules of step 2 and 3, the local terminal equipment maps every three time-slots of t1 payload data into four e1 time-slots. the mapping of t1 frame into e1 framing format is s hown in the table below. t able 174: t he mapping of t1 frame into e1 framing format t1 f-bit ts0 ts1 ts2 don't care bits ts3 ts4 ts5 e1 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 t1 don't care bits ts6 ts7 ts8 don't care bits ts9 ts10 ts1 1 e1 ts8 ts9 ts10 ts11 ts12 ts13 ts14 ts15 t1 don't care bits ts12 ts13 ts14 don't care bits ts15 ts1 6 ts17 e1 ts16 ts17 ts18 ts19 ts20 ts21 ts22 ts23 t1 don't care bits ts18 ts19 ts20 don't care bits ts21 ts2 2 ts23 e1 ts24 ts25 ts26 ts27 ts28 ts29 ts30 ts31
xrt86l30 212 rev. 1.0.1 single t1/e1/j1 framer/liu combo 11.2.2 non-multiplexed high-speed mode when the back-plane interface data rate is mvip 2.0 48mbit/s, 4.096mbit/s and 8.192mbit/s, the interfac e signals are all configured as inputs, except the re ceive serial data on rxser and the multi frame sync pulse provided by the framer. the transmit serial clock for each channel is always an input clock with freq uency of 1.544 mhz for all data rates so that it may be used as the timing reference for the transmit line rate . the txmsync signal is configured as the transmit input clock with frequencies of 2.048 mhz, 4.096 mhz and 8.192 mhz respectively. it serves as the primary cl ock source for the high-speed back-plane interface. figure 83 shows how to connect the transmit non-multiplexed high-speed input interface block to local terminal equipment. figure 84 shows how to connect the receive non-multiplexed h igh-speed output interface to local terminal equipment. f igure 83. t ransmit n on -m ultiplexed h igh -s peed c onnection to local terminal equipment using mvip 2.048m bit / s , 4.096m bit / s , or 8.192m bit / s f igure 84. r eceive n on -m ultiplexed h igh -s peed c onnection to local terminal equipment using mvip 2.048m bit / s , 4.096m bit / s , or 8.192m bit / s txserclk0 txser0 txmsync0 txsync0 transmit payload data input interface chn 0 terminal equipment xrt86l30 txmsync = 2.048/4.096/8.192mhz rxserclk0 rxser0 rxmsync0 rxsync0 receive payload data input interface chn 0 terminal equipment xrt86l30 rxmsync = 2.048/4.096/8.192mhz
xrt86l30 213 single t1/e1/j1 framer/liu combo rev. 1.0.1 figure 85 shows the waveforms for connecting the transmit no n-multiplexed high-speed input interface block to local terminal equipment. figure 86 shows the waveforms for connecting the receive non -multiplexed high-speed input interface block to local terminal equipment. f igure 85. w aveforms for c onnecting the t ransmit n on -m ultiplexed h igh -s peed i nput i nterface at mvip 2.048m bit / s , 4.096m bit / s , and 8.192m bit / s f igure 86. w aveforms for c onnecting the r eceive n on -m ultiplexed h igh -s peed i nput i nterface at mvip 2.048m bit / s , 4.096m bit / s , and 8.192m bit / s txserclk (1.5 mhz) txserclk (inv) txser txsync(input) txchclk(inv) txchn[0]/txsig txchn[1]/txfrtd f 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 c a b d don't care c a b d don't care c a b d don't care don't care c a b d don't care note: the following signals are not aligned with t he signals shown above. the txtsclk is derived from 1.544mhz transmit clock. don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 txmsync (2/4/8mhz) don't care don't care rxser rxsync(input) rxchclk(inv) rxchn[0]/rxsig rxchn[1]/rxfrtd f 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 c a b d don't care c a b d don't care c a b d don't care c a b d don't care note: the following signals are not aligned with t he signals shown above. the rxtsclk is derived from 1.544mhz transmit clock. don't care 8 7 6 5 4 3 2 1 don't care 8 7 6 5 4 3 2 1 don't care don't care don't care rxserclk (2/4/8mhz)
xrt86l30 214 rev. 1.0.1 single t1/e1/j1 framer/liu combo 11.2.3 multiplexed high-speed mode when the back-plane interface data rate is 12.352mb it/s, 16.384mbit/s, hmvip 16.384mbit/s, and h.100 16.384mbit/s, the interface signals are all configu red as inputs, except the receive serial data on rx ser and the multi frame sync pulse provided by the framer. the back-plane interface is processing data throug h txser0 or txser4 pins at 12.352mbit/s or 16.384mbit /s. the local terminal equipment multiplexes paylo ad and signaling data of every four channels into one serial data stream. payload and signaling data of c hannel 0- 3 are multiplexed onto the transmit serial data pin of channel 0. payload and signaling data of channe l 4-7 are multiplexed onto the transmit serial data pin o f channel 4. free-running clocks of 12.352mhz are supplied to the transmit input clock pin of channel 0 and channel 4 of the framer. the local terminal equipment provides multiplexed payload data at risi ng edge of this transmit input clock. the transmit high- speed back-plane interface of the framer then latch es incoming serial data at falling edge of the cloc k. the local terminal equipment maps four 1.544mbit/s ds1 data streams into one 12.352mbit/s serial data stre am as described below: 1. the f-bit of four channels are repeated and grouped together to form the first octet of the multiplexe d data stream. the f-bit of channel 0 is sent first, follo wed by f-bit of channel 1 and 2. the f-bit of chann el 3 is sent last. the table below shows bit-pattern of the first octet. f x : f-bit of channel x 2. payload data of four channels are repeated and grou ped together in a bit-interleaved way. the first pa y- load bit of timeslot 0 of channel 0 is sent first, followed by the first payload bit of timeslot 0 of channel 1 and 2. the first payload bit of timeslot 0 of chann el 3 is sent last. after the first bits of timeslot 0 of all four channels are sent, it comes the second bit of times lot 0 of channel 0 and so on. the table below demon - strates how payload bits of four channels are mappe d into the 12.352mbit/s data stream. x y : the xth payload bit of channel y 3. the local terminal equipment also multiplexes signa ling bits with payload bits and sends them together through the 12.352mbit/s data stream. when the term inal equipment is sending the fifth payload bit of each channel, instead of sending it twice, it inser ts the signaling bit a of that corresponding channe l. simi- larly, the sixth payload bit of a each channel is f ollowed by the signaling bit b of that channel; the seventh payload bit is followed by the signaling bit c; the eighth payload bit is followed by the signaling bi t d. first octet of 12.352mbit/s data stream b it 0 b it 1 b it 2 b it 3 b it 4 b it 5 b it 6 b it 7 f 0 f 0 f 1 f 1 f 2 f 2 f 3 f 3 second octet of 12.352mbit/s data stream b it 0 b it 1 b it 2 b it 3 b it 4 b it 5 b it 6 b it 7 1 0 1 0 1 1 1 1 1 2 1 2 1 3 1 3 third octet of 12.352mbit/s data stream b it 0 b it 1 b it 2 b it 3 b it 4 b it 5 b it 6 b it 7 2 0 2 0 2 1 2 1 2 2 2 2 2 3 2 3
xrt86l30 215 single t1/e1/j1 framer/liu combo rev. 1.0.1 the following table illustrates how payload bits an d signaling bits are multiplexed together into the 12.352mbit/ s data stream. x y : the xth payload bit of channel y a y : the signaling bit a of channel y 4. following the same rules of step 2 and 3, the local terminal equipment continues to map the payload da ta and signaling data of four channels into a 12.352mb it/s data stream. the transmit single-frame synchronization signal of channel 0 pulses high for one clock cycle at the f irst bit position (f-bit of channel 0) of the multiplexed da ta stream with data from channel 0-3 multiplexed to gether. the transmit single-frame synchronization signal of channel 4 pulses high for one clock cycle at the f irst bit position (f-bit of channel 4) of the data stream wi th data from channel 4-7 multiplexed together. by s ampling the high pulse on the transmit single-frame synchro nization signal, the framer can position the beginn ing of the multiplexed ds1 frame. it is responsibility of the terminal equipment to align the multiplexed tra nsmit serial data with the transmit single-frame synchronization pulse. inside the framer, all the "don't care" bits will b e stripped away. the framing bits, signaling and pa yload data are de-multiplexed inside the xrt86l30 and sent to each individual channel. these data will be processed b y each individual framer and send to the liu interfac e. the local terminal equipment provides a free-run ning 1.544mhz clock to the transmit serial input clock o f each channel. the framer will use this clock to c arry the processed payload and signaling data to the transmi t section of the device. figure 87 shows how to connect the transmit multiplexed high-speed input interface block to local terminal equipment. figure 88 shows how to connect the receive multiplexed high-speed outpu t interface to local terminal equipment. sixth octet of 12.352mbit/s data stream b it 0 b it 1 b it 2 b it 3 b it 4 b it 5 b it 6 b it 7 5 0 a 0 5 1 a 1 5 2 a 2 5 3 a 3 seventh octet of 12.352mbit/s data stream b it 0 b it 1 b it 2 b it 3 b it 4 b it 5 b it 6 b it 7 6 0 b 0 6 1 b 1 6 2 b 2 6 3 b 3 eighth octet of 12.352mbit/s data stream b it 0 b it 1 b it 2 b it 3 b it 4 b it 5 b it 6 b it 7 7 0 c 0 7 1 c 1 7 2 c 2 7 3 c 3 ninth octet of 12.352mbit/s data stream b it 0 b it 1 b it 2 b it 3 b it 4 b it 5 b it 6 b it 7 8 0 d 0 8 1 d 1 8 2 d 2 8 3 d 3
xrt86l30 216 rev. 1.0.1 single t1/e1/j1 framer/liu combo f igure 87. i nterfacing xrt86l30 t ransmit to local terminal equipment using 16.384m bit / s , hmvip 16.384m bit / s , and h.100 16.384m bit / s txser0 txmsync0 (12/16mhz) txsync0 txserclk0 (2.048mhz) transmit payload data input interface chn 0 terminal equipment xrt86l30
xrt86l30 217 single t1/e1/j1 framer/liu combo rev. 1.0.1 figure 89 shows the waveforms for connecting the transmit mu ltiplexed high-speed input interface block to local terminal equipment at 12.352mbit/s. figure 91 shows the waveforms for connecting the transmit multiplexed high-speed input interface block to loc al terminal equipment for 16.384mbit/s. figure 95 shows the waveforms for connecting the transmit multiplex ed high-speed input interface block to local termin al equipment for hmvip and h.100. figure 92 shows the waveforms for connecting the receive mul tiplexed high-speed input interface block to local terminal equipment for 12.352mhz. figure 93 shows the waveforms for connecting the receive multiplexed high-speed i nput interface block to local terminal equipment fo r 16.384mhz. figure 94 shows the waveforms for connecting the receive mul tiplexed high-speed input interface block to local terminal equipment for hmv ip 16.384mhz. figure 95 shows the waveforms for connecting the receive multiplexed high-speed input interface block to local terminal equipment for h. 100 16.384mhz. f igure 88. i nterfacing xrt86l30 r eceive to local terminal equipment using 16.384m bit / s , hmvip 16.384m bit / s , and h.100 16.384m bit / s f igure 89. w aveforms for c onnecting the t ransmit m ultiplexed h igh -s peed i nput i nterface at 12.352m bit / s mode rxser0 rxserclk0 (12/16mhz) rxsync0 rxlineclk0 (2.048mhz) transmit payload data input interface chn 0 terminal equipment xrt86l30 txinclk (12.352mhz) txinclk (inv) txser txsync(input) f 0 f 0 f 1 f 1 f 2 f 2 f 3 f 3 1 0 x 1 1 x x x 1 2 1 3 2 0 x 2 1 x x 3 0 4 0 x 5 0 a 0 5 1 a 1 5 2 a 2 5 3 a 3 6 0 b 0 6 1 b 1 6 2 b 2 6 3 b 3
xrt86l30 218 rev. 1.0.1 single t1/e1/j1 framer/liu combo . f igure 90. w aveforms for c onnecting the t ransmit m ultiplexed h igh -s peed i nput i nterface at 16.384m bit / s mode f igure 91. w aveforms for c onnecting the t ransmit m ultiplexed h igh -s peed i nput i nterface at hmvip and h.100 16.384m bit / s mode f igure 92. w aveforms for c onnecting the r eceive m ultiplexed h igh -s peed i nput i nterface at 12.352m bit / s mode txinclk (16.384mhz) txinclk (inv) txser txsync(input) f 0 f 0 f 1 f 1 f 2 f 2 f 3 f 3 1 0 x 1 1 x x x 1 2 1 3 2 0 x 2 1 x x 3 0 4 0 x 5 0 a 0 5 1 a 1 5 2 a 2 5 3 a 3 56 cycles txinclk (16.384mhz) txinclk (inv) txser 1 2 1 2 5 2 5 2 1 0 1 0 2 0 2 0 3 0 4 0 3 0 4 0 5 0 5 0 6 0 6 0 7 3 7 3 8 3 8 3 f 0 f 0 f 0 f 0 f 0 f 0 f 0 f 0 56 cycles 5 3 5 3 6 3 6 3 7 3 7 3 8 3 8 3 0 0 a 2 a 2 0 0 0 0 0 a 0 0 a 0 b 0 b 0 c 3 c 3 d 3 d 3 1 1 1 1 1 1 1 1 56 cycles a 3 a 3 b 3 b 3 c 3 c 3 d 3 d 3 txsig txsync(input) hmvip, negative sync txsync(input) hmvip, positive sync start of frame x y : x is the bit number and y is the channel number txsync(input) h.100, negative sync txsync(input) h.100, positive sync delayer h.100 txsync(input) h.100, negative sync txsync(input) h.100, positive sync 0 0 rxserclk (12.352mhz) rxserclk (inv) rxser rxsync(input) f 0 f 0 f 1 f 1 f 2 f 2 f 3 f 3 1 0 x 1 1 x x x 1 2 1 3 2 0 x 2 1 x x 3 0 4 0 x 5 0 a 0 5 1 a 1 5 2 a 2 5 3 a 3 6 0 b 0 6 1 b 1 6 2 b 2 6 3 b 3
xrt86l30 219 single t1/e1/j1 framer/liu combo rev. 1.0.1 f igure 93. w aveforms for c onnecting the r eceive m ultiplexed h igh -s peed i nput i nterface at 16.384m bit / s mode f igure 94. w aveforms for c onnecting the r eceive m ultiplexed h igh -s peed i nput i nterface at hmvip 16.384m bit / s mode f igure 95. w aveforms for c onnecting the r eceive m ultiplexed h igh -s peed i nput i nterface at h.100 16.384m bit / s mode rxserclk (16.384mhz) rxserclk (inv) rxser rxsync(input) f 0 f 0 f 1 f 1 f 2 f 2 f 3 f 3 1 0 x 1 1 x x x 1 2 1 3 2 0 x 2 1 x x 3 0 4 0 x 5 0 a 0 5 1 a 1 5 2 a 2 5 3 a 3 56 cycles rxserclk (16.384mhz) rxserclk (inv) rxser 1 2 1 2 5 2 5 2 1 0 1 0 2 0 2 0 3 0 4 0 3 0 4 0 5 0 5 0 6 0 6 0 7 3 7 3 8 3 8 3 f 0 f 1 f 0 f 1 f 2 f 2 f 3 f 3 56 cycles 5 3 5 3 6 3 6 3 7 3 7 3 8 3 8 3 0 0 a 2 a 2 0 0 0 0 0 0 0 0 a 0 a 0 b 0 b 0 c 3 c 3 d 3 d 3 1 1 1 1 1 1 1 1 56 cycles a 3 a 3 b 3 b 3 c 3 c 3 d 3 d 3 rxsig rxsync(input) hmvip, negative sync rxsync(input) hmvip, positive sync start of frame x y : x is the bit number and y is the channel number rxserclk (16.384mhz) rxserclk (inv) rxser 1 2 1 2 5 2 5 2 1 0 1 0 2 0 2 0 3 0 4 0 3 0 4 0 5 0 5 0 6 0 6 0 7 3 7 3 8 3 8 3 f 0 f 1 f 0 f 1 f 2 f 2 f 3 f 3 56 cycles 5 3 5 3 6 3 6 3 7 3 7 3 8 3 8 3 0 0 a 2 a 2 0 0 0 0 0 0 0 0 a 0 a 0 b 0 b 0 c 3 c 3 d 3 d 3 1 1 1 1 1 1 1 1 56 cycles a 3 a 3 b 3 b 3 c 3 c 3 d 3 d 3 rxsig start of frame x y : x is the bit number and y is the channel number rxsync(input) h.100, negative sync rxsync(input) h.100, positive sync delayer h.100 rxsync(input) h.100, negative sync rxsync(input) h.100, positive sync
xrt86l30 220 rev. 1.0.1 single t1/e1/j1 framer/liu combo 11.3 brief discussion of robbed-bit signaling in ds1 framing format signaling is required when dealing with voice and d ial-up data services in ds1 applications. tradition ally, signaling is provided on a dial-up telephone line, across the talk-path. bit robbing, or stealing the least significant bit (8th bit) in each of the twenty-fou r voice channels in the signaling frames allows eno ugh bits to signal between the transmitting and receiving end. that is where the name robbed-bit signaling comes f rom. these ends can be cpe to central office (co) for sw itched services, or cpe to cpe for pbx-to-pbx connections. signaling is used to tell the receiver where the ca ll or route is destined. the signal is sent through switches along the route to a distant end. common types of s ignals are: on hook off hook dial tone dialed digits ringing cycle busy tone robbed-bit signaling is supported in three ds1 fram ing formats. super-frame (sf) slc?96 extended super-frame (esf) in super-frame or slc?96 framing mode, frame number 6 and frame number 12 are signaling frames. in channelized ds1 applications, these frames are used to contain the signaling information. in frame num ber 6 and 12, the least significant bit of all twenty-fou r timeslots is 'robbed' to carry call state informa tion. the bit in frame 6 is called the a bit and the bit in frame 12 is called the b bit. the combination of a and b de fines the state of the call for the particular timeslot that these two bits are located in. in extended super-frame framing mode, frame number 6, 12, 18 and 24 are signaling frames. in these frames, the least significant bit of all twenty-fou r timeslots is 'robbed' to carry call state informa tion. the bit in frame 6 is called the a bit, the bit in frame 12 is called the b bit, the bit in frame 18 is called th e c bit and the bit in frame 24 is called the d bit. the combination of a, b, c and d defines the state of the call for th e particular timeslot that these signaling bits are located in. 11.3.1 configure the framer to transmit robbed-bit s ignaling the xrt86l30 framer supports transmission of robbed -bit signaling in esf, sf and slc?96 framing formats. signaling bits can be inserted into the ou tgoing ds1 frame through the following: signaling data is inserted from transmit signaling control registers (tscr) of each timeslot signaling data is inserted from txsig_n pin f rame n umber s ignaling b it 6 a 12 b f rame n umber s ignaling b it 6 a 12 b 18 c 24 d
xrt86l30 221 single t1/e1/j1 framer/liu combo rev. 1.0.1 signaling data is embedded into the input pcm data coming from the terminal equipment 11.3.2 insert signaling bits from tscr register the four most significant bits of the transmit sign aling control register (tscr) of each timeslot can be used to store outgoing signaling data. the user can prog ram these bits through the microprocessor access. i f the xrt86l30 framer is configured to insert signaling b its from the tscr registers, the ds1 transmit frame r block will strip off the least significant bits of each time slot in the signaling frames and replace it with the signaling bit stored inside the tscr registers. the insertion of signaling bits into pcm data is done on a per- channel basis. in sf or slc?96 mode, the user can control the xrt8 6l30 framer to transmit no signaling (transparent), two- code signaling, or four-code signaling. two-code si gnaling is done by substituting the least significa nt bit (lsb) of the specific channel in frame 6 and 12 with the content of the signaling bit a of the specific tscr register. four-code signaling is done by substituting the lsb of channel data in frame 6 with the signaling bit a and the lsb of channel data in frame 12 with the signaling bit b of the specific channel's tscr register. if s ixteen-code signaling is selected in sf format, only the signal ing bit a and signaling bit b information are used. in esf mode, the user can control the xrt86l30 fram er to transmit no signaling (transparent) by disabl e signaling insertion, two-code signaling, four-code signaling or sixteen code signaling. two-code signa ling is done by substituting the least significant bit (lsb ) of the specific channel in frame 6, 12, 18 and 24 with the content of the signaling bit a of the specific tscr register. four-code signaling is done by substituting the lsb of channel data in frame 6 and frame 18 with the s ignaling bit a and the lsb of channel data in frame 12 and f rame 24 with the signaling bit b of the specific ch annel's tscr register. sixteen-code signaling is implemented by substituti ng the lsb of channel data in frames 6, 12, 18, and 24 with the content of signaling bit a, b, c, and d of tscr register respectively. in n or t1dm modes, no robbed-bit signaling is allo wed and the transmit data stream remains intact. the table below shows the four most significant bit s of the transmit signaling control register. 11.3.3 insert signaling bits from txsig_n pin the xrt86l30 framer can be configured to insert sig naling bits provided by external equipment through the txsig_n pins. this pin is a multiplexed i/o pin wit h two functions: txchn[0]_n - transmit timeslot number bit [0] outpu t pin txsig_n - transmit signaling input pin when the transmit fractional ds1 bit of the transmi t interface control register (ticr) is set to 0, th is pin is configured as txtsb[0]_n pin, it outputs bit 0 of t he timeslot number of the ds1 pcm data that is tran smitting. transmit signaling control register (tscr) (addres s = 0x0340h - 0x0357h) b it n umber b it n ame b it t ype b it d escription 7 signaling bit a r/w this bit is used to store signal ing bit a that is sent as the least significant bit of timeslot of frame number 6. 6 signaling bit b r/w this bit is used to store signal ing bit b that is sent as the least significant bit of timeslot of frame number 12. 5 signaling bit c r/w this bit is used to store signal ing bit c that is sent as the least significant bit of timeslot of frame number 18. 4 signaling bit d r/w this bit is used to store signal ing bit d that is sent as the least significant bit of timeslot of frame number 24.
xrt86l30 222 rev. 1.0.1 single t1/e1/j1 framer/liu combo when the transmit fractional ds1 bit of the transmi t interface control register (ticr) is set to 1, th is pin is configured as txsig_n pin, it acts as an input sour ce for the signaling bits to be transmitted in the outbound ds1 frames. figure 96 below is a timing diagram of the txsig_n input pin . please note that the signaling bit a of a certain timeslot coincides with bit 4 of the pcm data; sign aling bit b coincides with bit 5 of the pcm data; s ignaling bit c coincides with bit 6 of the pcm data and signalin g bit d coincides with bit 7 (lsb) of the pcm data. the table below shows configurations of the transmi t fractional ds1 bit of the transmit interface cont rol register (ticr). f igure 96. t iming d iagram of the t x s ig _ n i nput transmit interface control register (ticr)(address = 0x0120h) b it n umber b it n ame b it t ype b it d escription 4 transmit fractional ds1 r/w this read/write bit-field permits the user to de termine which one of the two functions the multiplexed i/o pin of txtsb[0]_n /txsig_n is spotting. 0 - this pin is configured as txtsb[0]_n pin, it ou tputs bit 0 of the timeslot number of the ds1 pcm data that is transmitting. 1 - this pin is configured as txsig_n pin, it acts as an input source for the signaling bits to be transmitted in the outbound ds 1 frames
xrt86l30 223 single t1/e1/j1 framer/liu combo rev. 1.0.1 12.0 alarms and error conditions the xrt86l30 t1/j1/e1 quad framer can be configured to monitor quality of received ds1 frames. it can generate error indicators if the local receive fram er has received error frames from the remote termin al. if corresponding interrupt is enabled, the local micro processor operation is interrupted by these error c onditions. upon microprocessor interruption, the user can inte rvene by looking into the error conditions. at the same time, the user can configure the xrt86l 30 framer to transmit alarms and error indications to remote terminal. different alarms and error indicat ions will be transmitted depending on the error con dition. the section below gives a brief discussion of the e rror conditions that can be detected by the xrt86l3 0 framer and error indications that will be generated . 12.1 ais alarm as we discussed before, transmission of alarm indic ation signal (ais) or blue alarm by the intermediat e node indicates that the equipment is still functioning b ut unable to offer services. it is an all ones (exc ept for framing bits) pattern which can be used by the equipment fu rther down the line to maintain clock recovery and timing synchronization. the xrt86l30 framer can detect two types of ais in ds1 mode: framed ais unframed ais unframed ais is an all ones pattern. if unframed ai s is sent, the equipment further down the line will be able to maintain timing synchronization and be able to reco ver clock from the received ais signal. however, du e to the lack of framing bits, the equipment farther down th e line will not be able to maintain frame synchroni zation and will declare loss of frame (lof). on the other hand, the payload portion of a framed ais pattern is all ones. however, a framed ais patt ern still has correct framing bits. therefore, the equipment further down the line can still maintain frame synchronization as well as timing synchronization. in this case, no lof or red alarm will be declared. the alarm indication logic within the receive frame r block of the xrt86l30 framer monitors the incomin g ds1 frames for ais. ais alarm condition are detecte d and declared according to the following procedure : 1. the incoming ds1 frames are monitored for ais detec tion. ais detection is defined as an unframed or framed pattern with less than three zeros in two co nsecutive frames. 2. an ais detection counter within the receive framer block of the xrt86l30 counts the occurrences of ais detection over a 6 ms interval. it will indicate a valid ais flag when twenty-two or more of a possibl e twenty- four ais are detected. 3. each 6 ms interval with a valid ais flag increments a flag counter which declares ais alarm when 255 v alid flags have been collected. therefore, ais condition has to be persisted for 1. 53 seconds before ais alarm condition is declared b y the xrt86l30 framer. if there is no valid ais flag over a 6ms interval, the alarm indication logic will decrement the flag counter. the ais alarm is removed when the counter reaches 0. t hat is, ais alarm will be removed if over 1.53 seco nds, there is no valid ais flag.
xrt86l30 224 rev. 1.0.1 single t1/e1/j1 framer/liu combo the alarm indication signal detection select bits o f the alarm generation register (agr) enable the tw o types of ais detection that are supported by the xrt86l30 framer. the table below shows configurations of th e alarm indication signal detection select bits of th e alarm generation register (agr). if detection of unframed or framed ais alarm is ena bled by the user and if ais is present in the incom ing ds1 frame, the xrt86l30 framer can generate a receive a is state change interrupt associated with the setti ng of receive ais state change bit of the alarm and error status register to one. to enable the receive ais state change interrupt, t he receive ais state change interrupt enable bit of the alarm and error interrupt enable register (aeier) h ave to be set to one. in addition, the alarm and er ror interrupt enable bit of the block interrupt enable register (bier) needs to be one. the table below shows configurations of the receive ais state change interrupt enable bit of the alarm and error interrupt enable register (aeier). the table below shows configurations of the alarm a nd error interrupt enable bit of the block interrup t enable register. when these interrupt enable bits are set and ais is present in the incoming ds1 frame, the xrt86l30 fr amer will declare ais by doing the following: set the read-only receive ais state bit of the alar m and error status register (aesr) to one indicatin g there is ais alarm detected in the incoming ds1 fra me. set the receive ais state change bit of the alarm a nd error status register to one indicating there is a change in state of ais. this status indicator is va lid until the framer interrupt status register is r ead. reading this register clears the associated interru pt if reset-upon-read is selected in interrupt cont rol register (icr). otherwise, a write-to-clear operati on by the microprocessor is required to reset these status indicators. alarm generation register (agr) (address = 0x0108h ) b it n umber b it n ame b it t ype b it d escription 1-0 ais detection select r/w 00 - ais alarm detection is disabled.when this b it is set to 01:detection of unframed ais alarm of all ones pattern is enabled. 10 - ais alarm detection is disabled.when this bit is set to 00:detection of framed ais alarm of all ones pattern except for fra ming bits is enabled. alarm and error interrupt enable register (aeier) (address = 0x0b03h) b it n umber b it n ame b it t ype b it d escription 1 receive ais state change interrupt enable r/w 0 - the receive ais state change interrupt is di sabled. 1 - the receive ais state change interrupt is enab led. block interrupt enable register (bier) (address = 0x0b01h) b it n umber b it n ame b it t ype b it d escription 1 alarm and error interrupt enable r/w 0 - every interrupt generated by the alarm and e rror interrupt status reg- ister (aeisr) is disabled. 1 - every interrupt generated by the alarm and erro r interrupt status reg- ister (aeisr) is enabled.
xrt86l30 225 single t1/e1/j1 framer/liu combo rev. 1.0.1 the table below shows the receive ais state change status bits of the alarm and error status register. the receive ais state bit of the alarm and error st atus register (aesr), on the other hand, is a read- only bit indicating there is ais alarm detected in the incom ing ds1 frame. the table below shows the receive ais state status bits of the alarm and error status register. 12.2 red alarm the alarm indication logic within the receive frame r block of the xrt86l30 framer monitors the incomin g ds1 frames for red alarm or loss of frame (lof) con dition. red alarm condition are detected and declar ed according to the following procedure: 1. the red alarm is detected by monitoring the occurre nce of loss of frame (lof) over a 6 ms interval. 2. an lof valid flag will be posted on the interval wh en one or more lof occurred during the interval. 3. each interval with a valid lof flag increments a fl ag counter which declares red alarm when 63 valid intervals have been accumulated. 4. an interval without valid lof flag decrements the f lag counter. the red alarm is removed when the counter reaches zero. if lof condition is present in the incoming ds1 fra me, the xrt86l30 framer can generate a receive red alarm state change interrupt associated with the se tting of receive red alarm state change bit of the alarm and error status register to one. to enable the receive red alarm state change interr upt, the receive red alarm state change interrupt enable bit of the alarm and error interrupt enable register (aeier) has to be set to one. in addition, the alarm and error interrupt enable bit of the block interru pt enable register (bier) needs to be one. the table below shows configurations of the receive red alarm state change interrupt enable bit of the alarm and error interrupt enable register (aeier). alarm and error status register (aesr) (address = 0 x0b02h) b it n umber b it n ame b it t ype b it d escription 1 receive ais state change rur / wc 0 - there is no change of ais state in the incoming ds1 payload data. 1 - there is change of ais state in the incoming ds 1 payload data. alarm and error status register (aesr) (address = 0x0b02h) b it n umber b it n ame b it t ype b it d escription 6 receive ais state r 0 - there is no ais alarm condit ion detected in the incoming ds1 payload data. 1 - there is ais alarm condition detected in the in coming ds1 payload data. alarm and error interrupt enable register (aeier) (address = 0x0b03h) b it n umber b it n ame b it t ype b it d escription 2 receive red alarm state change interrupt enable r/w 0 - the receive red alarm state change interrupt is disabled. no receive loss of frame (rxlof) interrupt will be generated u pon detection of lof condition. 1 - the receive red alarm state change interrupt is enabled. receive loss of frame (rxlof) interrupt will be generated u pon detection of lof condition.
xrt86l30 226 rev. 1.0.1 single t1/e1/j1 framer/liu combo the table below shows configurations of the alarm a nd error interrupt enable bit of the block interrup t enable register. when these interrupt enable bits are set and red al arm is present in the incoming ds1 frame, the xrt86 l30 framer will declare red alarm by doing the followin g: set the read-only receive red alarm state bit of th e alarm and error status register (aesr) to one indicating there is red alarm detected in the incom ing ds1 frame. set the receive red alarm state change bit of the a larm and error status register to one indicating th ere is a change in state of red alarm. this status indicat or is valid until the framer interrupt status regis ter is read. reading this register clears the associated interru pt if reset-upon-read is selected in interrupt cont rol register (icr). otherwise, a write-to-clear operati on by the microprocessor is required to reset these status indicators. the table below shows the receive red alarm state c hange status bits of the alarm and error status register. the receive red alarm state bit of the alarm and er ror status register (aesr), on the other hand, is a read- only bit indicating there is red alarm detected in the incoming ds1 frame. the table below shows the receive red alarm state s tatus bits of the alarm and error status register. 12.3 yellow alarm the alarm indication logic within the receive frame r block of the xrt86l30 framer monitors the incomin g ds1 frames for yellow alarm condition. the yellow a larm is detected and declared according to the foll owing procedure: 1. monitor the occurrence of yellow alarm pattern over a 6 ms interval. a yel valid flag will be posted on the interval when yellow alarm pattern occurred during the interval. block interrupt enable register (bier) (address = 0 x0b01h) b it n umber b it n ame b it t ype b it d escription 1 alarm and error interrupt enable r/w 0 - every interrupt generated by the alarm and e rror interrupt status reg- ister (aeisr) is disabled. 1 - every interrupt generated by the alarm and erro r interrupt status reg- ister (aeisr) is enabled. alarm and error status register (aesr) (address = 0 x0b02h) b it n umber b it n ame b it t ype b it d escription 2 receive red alarm state change rur / wc 0 - there is no change of red alarm state in the in coming ds1 payload data. 1 - there is change of red alarm state in the incom ing ds1 payload data. alarm and error status register (aesr) (address = 0 x0b02h) b it n umber b it n ame b it t ype b it d escription 7 receive red alarm state r 0 - there is no red alarm condition detected in th e incoming ds1 payload data. 1 - there is red alarm condition detected in the in coming ds1 payload data.
xrt86l30 227 single t1/e1/j1 framer/liu combo rev. 1.0.1 2. each interval with a valid yel flag increments a fl ag counter which declares yel alarm when 80 valid intervals have been accumulated. 3. an interval without valid yel flag decrements the f lag counter. the yel alarm is removed when the counter reaches zero. if yellow alarm condition is present in the incomin g ds1 frame, the xrt86l30 framer can generate a rec eive yellow alarm state change interrupt associated with the setting of receive yellow alarm state change b it of the alarm and error status register to one. to enable the receive yellow alarm state change int errupt, the receive yellow alarm state change inter rupt enable bit of the alarm and error interrupt enable register (aeier) has to be set to one. in addition, the alarm and error interrupt enable bit of the block interru pt enable register (bier) needs to be one. the table below shows configurations of the receive yellow alarm state change interrupt enable bit of the alarm and error interrupt enable register (aeier). the table below shows configurations of the alarm a nd error interrupt enable bit of the block interrup t enable register. when these interrupt enable bits are set and yellow alarm is present in the incoming ds1 frame, the xrt86l30 framer will declare yellow alarm by doing the following: set the read-only receive yellow alarm state bit of the alarm and error status register (aesr) to one indicating there is yellow alarm detected in the in coming ds1 frame. set the receive yellow alarm state change bit of th e alarm and error status register to one indicating there is a change in state of yellow alarm. this status i ndicator is valid until the framer interrupt status register is read. reading this register clears the associated interru pt if reset-upon-read is selected in interrupt cont rol register (icr). otherwise, a write-to-clear operati on by the microprocessor is required to reset these status indicators. alarm and error interrupt enable register (aeier) ( address = 0x0b03h) b it n umber b it n ame b it t ype b it d escription 0 receive yellow alarm state change interrupt enable r/w 0 - the receive yellow alarm state change interr upt is disabled. any state change of receive yellow alarm will not generate an interrupt. 1 - the receive yellow alarm state change interrupt is enabled. any state change of receive yellow alarm will generate an int errupt. block interrupt enable register (bier) (address = 0 x0b01h) b it n umber b it n ame b it t ype b it d escription 1 alarm and error interrupt enable r/w 0 - every interrupt generated by the alarm and e rror interrupt status reg- ister (aeisr) is disabled. 1 - every interrupt generated by the alarm and erro r interrupt status reg- ister (aeisr) is enabled.
xrt86l30 228 rev. 1.0.1 single t1/e1/j1 framer/liu combo the table below shows the receive yellow alarm stat e change status bits of the alarm and error status register. the table below shows the receive ais state change status bits of the alarm and error status register. the receive yellow alarm state bit of the alarm and error status register (aesr), on the other hand, i s a read-only bit indicating there is yellow alarm dete cted in the incoming ds1 frame. the table below shows the receive yellow alarm stat e status bits of the alarm and error status registe r. 12.4 bipolar violation the line coding for the ds1 signal should be bipola r. that is, a binary "0" is transmitted as zero vol ts while a binary "1" is transmitted as either a positive or n egative pulse, opposite in polarity to the previous pulse. a bipolar violation or bpv occurs when the alternate polarity rule is violated. the alarm indication log ic within the receive framer block of the xrt86l30 framer monitor s the incoming ds1 frames for bipolar violations. if a bipolar violation is present in the incoming d s1 frame, the xrt86l30 framer can generate a receiv e bipolar violation interrupt associated with the set ting of receive bipolar violation bit of the alarm and error status register to one. to enable the receive bipolar violation interrupt, the receive bipolar violation interrupt enable bit of the alarm and error interrupt enable register (aeier) has to be set to one. in addition, the alarm and error int errupt enable bit of the block interrupt enable register ( bier) needs to be one. the table below shows configurations of the receive bipolar violation interrupt enable bit of the alar m and error interrupt enable register (aeier). alarm and error status register (aesr)(address = 0x 0b02h) b it n umber b it n ame b it t ype b it d escription 0 receive yellow alarm state change rur / wc 0 - there is no change of yellow alarm state in the incoming ds1 payload data. 1 - there is change of yellow alarm state in the in coming ds1 payload data. alarm and error status register (aesr) (address = 0x0b02h) b it n umber b it n ame b it t ype b it d escription 5 receive yellow alarm state r 0 - there is no yellow alarm condition detected in the incoming ds1 pay- load data. 1 - there is yellow alarm condition detected in the incoming ds1 payload data. alarm and error interrupt enable register (aeier) (address = 0x0b03h) b it n umber b it n ame b it t ype b it d escription 3 receive bipolar violation interrupt enable r/w 0 - the receive bipolar violation interrupt is d isabled. occurrence of one or more bipolar violations will not generate an int errupt. 1 - the receive bipolar violation interrupt is enab led. occurrence of one or more bipolar violations will generate an interru pt.
xrt86l30 229 single t1/e1/j1 framer/liu combo rev. 1.0.1 the table below shows configurations of the alarm a nd error interrupt enable bit of the block interrup t enable register. when these interrupt enable bits are set and one or more bipolar violations are present in the incomin g ds1 frame, the xrt86l30 framer will declare receive bip olar violation by doing the following: set the receive bipolar violation bit of the alarm and error status register to one indicating there a re one or more bipolar violations. this status indicator is v alid until the framer interrupt status register is read. reading this register clears the associated interru pt if reset-upon-read is selected in interrupt cont rol register (icr). otherwise, a write-to-clear operati on by the microprocessor is required to reset these status indicators. the table below shows the receive bipolar violation status bits of the alarm and error status register . the table below shows configurations of the alarm a nd error interrupt enable bit of the block interrup t enable register. block interrupt enable register (bier) (address = 0 x0b01h) b it n umber b it n ame b it t ype b it d escription 1 alarm and error interrupt enable r/w 0 - every interrupt generated by the alarm and e rror interrupt status reg- ister (aeisr) is disabled. 1 - every interrupt generated by the alarm and erro r interrupt status reg- ister (aeisr) is enabled. alarm and error status register (aesr) (address = 0x0b02h) b it n umber b it n ame b it t ype b it d escription 3 receive bipolar violation state change rur / wc 0 - there is no change of bipolar violation state i n the incoming ds1 pay- load data. 1 - there is change of bipolar violation state in t he incoming ds1 payload data. alarm and error interrupt enable register (aeier) ( address = 0x0b03h) b it n umber b it n ame b it t ype b it d escription 4 receive loss of signal interrupt enable r/w 0 - the receive loss of signal interrupt is disa bled. occurrence of loss of signals will not generate an interrupt. 1 - the receive loss of signal interrupt is enabled . occurrence of loss of signals will generate an interrupt. block interrupt enable register (bier) (address = 0 x0b01h) b it n umber b it n ame b it t ype b it d escription 1 alarm and error interrupt enable r/w 0 - every interrupt generated by the alarm and e rror interrupt status reg- ister (aeisr) is disabled. 1 - every interrupt generated by the alarm and erro r interrupt status reg- ister (aeisr) is enabled.
xrt86l30 230 rev. 1.0.1 single t1/e1/j1 framer/liu combo when these interrupt enable bits are set and one or more loss of signals are present in the incoming d s1 frame, the xrt86l30 framer will declare receive los s of signal by doing the following: set the receive loss of signal bit of the alarm and error status register to one indicating there is o ne or more loss of signals. this status indicator is vali d until the framer interrupt status register is rea d. reading this register clears the associated interru pt if reset-upon-read is selected in interrupt cont rol register (icr). otherwise, a write-to-clear operati on by the microprocessor is required to reset these status indicators. the table below shows the receive loss of signal st atus bits of the alarm and error status register. alarm and error status register (aesr) (address = 0x0b02h) b it n umber b it n ame b it t ype b it d escription 4 receive loss of signal state rur / wc 0 - there is no change of loss of signal state in t he incoming ds1 payload data. 1 - there is change of loss of signal state in the incoming ds1 payload data.
xrt86l30 231 single t1/e1/j1 framer/liu combo rev. 1.0.1 12.5 e1 brief discussion of alarms and error conditi ons as defined in e1 specification, alarm conditions ar e created from defects. defects are momentary impai rments present on the e1 trunk. if a defect is present for a sufficient amount of time (called the integratio n time), then the defect becomes an alarm. once an alarm is decla red, the alarm is present until after the defect cl ears for a sufficient period of time. the time it takes to cle ar an alarm is called the de-integration time. alarms are used to detect and warn maintenance pers onnel of problems on the e1 trunk. there are three types of alarms: red alarm or service alarm indication (sai) signal blue alarm or alarm indication signal (ais) yellow alarm or remote alarm indication (rai) signa l to explain the error conditions and generation of d ifferent alarms, let us create a simple e1 system m odel. in this model, an e1 signal is sourced from the centra l office (co) through a repeater to the customer pr emises equipment (cpe). at the same time, an e1 signal is routed from the cpe to the repeater and back to the central office. figure 97 below shows the simple e1 system model. when the e1 system runs normally, that is, when the re is no loss of signal (los) or loss of frame (lof ) detected in the line, no alarm will be generated. s ometimes, intermittent outburst of electrical noise s on the line might result in bipolar violation or bit errors in the incoming signals, but these errors in general w ill not trigger the equipment to generate alarms. they will, depend ing on the system requirements, trigger the framer to generate interrupts that would cause the local micr oprocessor to create performance reports of the lin e. now, consider a case in which the e1 line from the co to the repeater is broken or interrupted, result ing in completely loss of incoming data or severely impair ed signal quality. upon detection of loss of signal (los) or loss of frame (lof) condition, the repeater will ge nerate an internal red alarm, also known as the ser vice alarm indication. this alarm will normally trigger a microprocessor interrupt informing the user that an incoming signal failure is happening. when the repeater is in the red alarm state, it wil l transmit the yellow alarm to the co indicating th e loss of an incoming signal or loss of frame synchronization . this yellow alarm informs the co that there is a problem f igure 97. s imple d iagram of e1 system model e1 receive framer block e1 transmit framer block e1 receive framer block e1 transmit framer block e1 transmit section e1 transmit section e1 receive section e1 receive section co repeater cpe simple e1 system model
xrt86l30 232 rev. 1.0.1 single t1/e1/j1 framer/liu combo further down the line and its transmission is not b eing received at the repeater. figure 98 below illustrates the scenario in which the e1 connection from the co to the repeater is broken. the repeater will also transmit a blue alarm, also known as alarm indication signal (ais) to the cpe. blue alarm is an all ones pattern indicating that the eq uipment is functioning but unable to offer service due to failures originated from remote side. it is sent su ch that the equipment downstream will not lose cloc k f igure 98. g eneration of y ellow a larm by the r epeater upon detection of line failure e1 receive framer block e1 transmit framer block e1 receive framer block e1 transmit framer block e1 transmit section e1 transmit section e1 receive section e1 receive section co repeater cpe the e1 line is broken repeater declares red alarm internally yellow alarm repeater generates yellow alarm to co
xrt86l30 233 single t1/e1/j1 framer/liu combo rev. 1.0.1 synchronization even though no meaningful data is r eceived. figure 99 below illustrates this scenario in which the repeater is sending an ais to the cpe upon dete ction of line failure from the co. now, the cpe uses the ais signal sent by the repeat er to recover received clock and remain in synchronization with the system. upon detecting the incoming ais signal, the cpe will generate a yello w alarm automatically to the repeater to indicate the loss of incoming data. figure 100 below illustrates this scenario in which the repeater is sending an ais to the cpe and the cpe is sending a yellow alarm back to the repeater. f igure 99. g eneration of ais by the r epeater upon detection of line failure e1 receive framer block e1 transmit framer block e1 receive framer block e1 transmit framer block e1 transmit section e1 transmit section e1 receive section e1 receive section co repeater cpe the e1 line is broken repeater declares red alarm internally yellow alarm repeater generates yellow alarm to co repeater generates ais to cpe ais
xrt86l30 234 rev. 1.0.1 single t1/e1/j1 framer/liu combo next, let us consider the scenario in which the sig naling and data link channel (the time slot 16) of an e1 line between a far-end terminal (for example, the co) an d a near-end terminal (for example, the repeater) i s impaired. in this case, the cas signaling data rece ived by the repeater is corrupted. the repeater wil l then send an all ones pattern in time slot 16 (ais16) do wnstream to the cpe. the repeater will also generat e a cas multi-frame yellow alarm upstream to the co to indi cate the loss of cas multi-frame synchronization. f igure 100. g eneration of y ellow a larm by the cpe upon detection of ais originated by the r epeater e1 receive framer block e1 transmit framer block e1 receive framer block e1 transmit framer block e1 transmit section e1 transmit section e1 receive section e1 receive section co repeater cpe the e1 line is broken repeater declares red alarm internally yellow alarm repeater generates yellow alarm to co repeater generates ais to cpe ais yellow alarm cpe detects ais and generates yellow alarm to repeater
xrt86l30 235 single t1/e1/j1 framer/liu combo rev. 1.0.1 figure 101 below illustrates this scenario in which the repea ter is sending an "ais16" pattern to the cpe while sending a cas multi-frame yellow alarm to the co. f igure 101. g eneration of cas m ulti - frame y ellow a larm and ais16 by the r epeater e1 receive framer block e1 transmit framer block e1 receive framer block e1 transmit framer block e1 transmit section e1 transmit section e1 receive section e1 receive section co repeater cpe the timeslot 16 of an e1 line is iimpaired repeater generates cas multi-frame yellow alarm to co repeater generates ais16 to cpe ais16 cas multi- frame yellow alarm
xrt86l30 236 rev. 1.0.1 single t1/e1/j1 framer/liu combo the cpe, upon detecting the incoming ais16 signal, will generate a cas multi-frame yellow alarm to the repeater to indicate the loss of cas multi-frame sy nchronization. figure 102 below illustrates the cpe sending a cas multi-frame yellow alarm back to the repeater in summary, ais or blue alarm is sent by a piece of e1 equipment downstream indicating that the incomi ng signal from upstream is lost. yellow alarm is sent by a piece of e1 equipment upstream upon detection of loss of signal, loss of frame or when it is receiving ai s. similarly, an "ais16" pattern is sent by a piece of e1 equipment downstream indicating that the incomi ng data link channel from upstream is damaged. the cas mult i-frame yellow alarm is sent by a piece of e1 equip ment upstream upon detection of loss of cas multi-frame synchronization or when it is receiving an "ais16" pattern. 12.5.1 how to configure the framer to transmit ais as we discussed in the previous section, alarm indi cation signal (ais) or blue alarm is transmitted by the intermediate node to indicate that the equipment is still functioning but unable to offer services. it is an all ones (except for framing bits) pattern which can be used by the equipment further down the line to maintain clock recovery and timing synchronization. the xrt86l30 framer can generate three types of ais when it is running in e1 format: framed ais unframed ais ais16 unframed ais is an all ones pattern. if unframed ai s is sent, the equipment further down the line will be able to maintain timing synchronization and be able to reco ver clock from the received ais signal. however, du e to the lack of framing bits, the equipment farther down th e line will not be able to maintain frame synchroni zation and will declare loss of frame (lof). f igure 102. g eneration of cas m ulti - frame y ellow a larm by the cpe upon detection of ais16 pattern sent by the r epeater e1 receive framer block e1 transmit framer block e1 receive framer block e1 transmit framer block e1 transmit section e1 transmit section e1 receive section e1 receive section co repeater cpe the timeslot 16 of an e1 line is iimpaired repeater generates cas multi-frame yellow alarm to co repeater generates ais16 to cpe ais16 cas multi- frame yellow alarm cpe detects ais16 and generates cas multi-frame yellow alarm to repeater cas multi- frame yellow alarm
xrt86l30 237 single t1/e1/j1 framer/liu combo rev. 1.0.1 on the other hand, the payload portion of a framed ais pattern is all ones. however, a framed ais patt ern still has correct framing bits. therefore, the equipment further down the line can still maintain frame synchronization as well as timing synchronization. in this case, no lof or red alarm will be declared. "ais16" is an ais alarm that is supported only in e 1 framing format. it is an all ones pattern in time slot 16 of each e1 frame. as we mentioned before, time slot 16 is usually used for signaling and data link in e1, therefore, an "ais16" alarm is transmitted by the i ntermediate node to indicate that the data link cha nnel is having a problem. since all the other thirty one ti me slots are still transmitting normal data (that i s, framing information and pcm data), the equipment further do wn the line can still maintain frame synchronizatio n, timing synchronization as well as receive pcm data. in this case, no lof or red alarm will be declared by the equipment further down the line. however, a cas mul ti-frame yellow alarm will be sent by the equipment further down the line to indicate the loss of cas m ulti-frame alignment. the transmit alarm indication signal select bits of the alarm generation register (agr) enable the thr ee types of ais transmission that are supported by the xrt86l30 framer. the table below shows configurati ons of the transmit alarm indication signal select bits of the alarm generation register (agr). 12.5.2 how to configure the framer to generate red a larm upon detection of loss of signal (los) or loss of f rame (lof) condition, the repeater will generate an internal red alarm when enabled. this alarm will no rmally trigger a microprocessor interrupt informing the user that an incoming signal failure is happening. the loss of frame declaration enable bit of the ala rm generation register (agr) enable the generation of red alarm. the table below shows configurations of the of frame declaration enable bit of the alarm generation register (agr). 12.5.3 how to configure the framer to transmit yello w alarm the xrt86l30 framer supports transmission of both y ellow alarm and cas multi-frame yellow alarm in e1 mode. alarm generation register (agr) (address = 0x0108h ) b it n umber b it n ame b it t ype b it d escription 3-2 transmit ais select r/w these read/write bit-fields allows the user to c hoose which one of the three ais pattern supported by the xrt86l30 framer will be transmitted. 00 - no ais alarm is generated. 01 - enable unframed ais alarm of all ones pattern. 11 - ais16 pattern is generated. only time slot 16 is carrying the all ones pattern. the other time slots still carry framing a nd pcm data. 11 - enable framed ais alarm of all ones pattern ex cept for framing bits. alarm generation register (agr) (address = 0x0108h ) b it n umber b it n ame b it t ype b it d escription 6 loss of frame declaration enable r/w this read/write bit-field permits the framer to declare red alarm in case of loss of frame alignment (lof). when receiver module of the framer detects loss of frame alignment in the incoming data stream, it will generate a red al arm. the framer will also generate an rxlofs interrupt to notify the mic roprocessor that an lof condition is occurred. a yellow alarm is then r eturned to the remote transmitter to report that the local receiver detec ts lof. 0 - red alarm declaration is disabled. 1 - red alarm declaration is enabled.
xrt86l30 238 rev. 1.0.1 single t1/e1/j1 framer/liu combo upon detection of loss of signal (los) or loss of f rame (lof) condition, the receiver will transmit th e yellow alarm back to the source indicating the loss of an incoming signal. this yellow alarm informs the sour ce that there is a problem further down the line and its tr ansmission is not being received at the destination . on the other hand, upon detection of loss of cas mu lti-frame alignment pattern, the receiver section o f the xrt86l30 framer will transmit a cas multi-frame yel low alarm back to the source indicating the loss of cas multi-frame synchronization. the yellow alarm generation select bits of the alar m generation register (agr) enable transmission of different types of yellow alarm that are supported by the xrt86l30 framer. 12.5.4 transmit yellow alarm the yellow alarm bits are located at bit 2 of time slot 0 of non-fas frames. a logic one of this bit d enotes the yellow alarm and a logic zero of this bit denotes n ormal operation. the xrt86l30 supports transmission of yellow alarm automatically or manually. when the yellow alarm generation select bits of the alarm generation register are set to 01, the yello w alarm bit is transmitted by echoing the received fas alig nment pattern. if the correct fas alignment is rece ived, the yellow alarm bit is set to zero. if the fas alignme nt pattern is missing or corrupted, the yellow alar m bit is set to one while loss of frame synchronization is decla red. when the yellow alarm generation select bits of the alarm generation register are set to 10, the yello w alarm bit is transmitted as zero. when the yellow alarm generation select bits of the alarm generation register are set to 11, the yello w alarm bit is transmitted as one. 12.5.5 transmit cas multi-frame yellow alarm within the sixteen-frame cas multi-frame, the cas m ulti-frame yellow alarm bits are located at bit 6 o f time slot 16 of frame number 0. a logic one of this bit denotes the cas multi-frame yellow alarm and a logi c zero of this bit denotes normal operation. the xrt86l30 sup ports transmission of cas multi-frame yellow alarm automatically or manually. when the cas multi-frame yellow alarm generation se lect bits of the alarm generation register are set to 01, the cas multi-frame yellow alarm bit is transmitted by echoing the received cas multi-frame alignment pattern (the four zeros pattern). if the correct cas multi- frame alignment is received, the cas multi-frame ye llow alarm bit is set to zero. if the cas multi-frame al ignment pattern is missing or corrupted, the cas mu lti-frame yellow alarm bit is set to one while loss of cas mu lti-frame synchronization is declared. when the cas multi-frame yellow alarm generation se lect bits of the alarm generation register are set to 10, the cas multi-frame yellow alarm bit is transmitted as zero. when the cas multi-frame yellow alarm generation se lect bits of the alarm generation register are set to 11, the cas multi-frame yellow alarm bit is transmitted as one.
xrt86l30 239 single t1/e1/j1 framer/liu combo rev. 1.0.1 12.6 t1 brief discussion of alarms and error conditi ons as defined in ansi t1.231 specification, alarm cond itions are created from defects. defects are moment ary impairments present on the ds1 trunk. if a defect i s present for a sufficient amount of time (called t he integration time), then the defect becomes an alarm . once an alarm is declared, the alarm is present u ntil after the defect clears for a specified period of time. t he time it takes to clear an alarm is called the de -integration time. alarms are used to detect and warn maintenance pers onnel of problems on the ds1 trunk. there are three types of alarms: red alarm or service alarm indication (sai) signal blue alarm or alarm indication signal (ais) yellow alarm or remote alarm indication (rai) signa l a simple ds1 system model is shown in figure 103 to explain the error conditions and generation of different alarms, let us create. in this model, a ds1 signal is sourced from the central office (co) through a r epeater to the customer premises equipment (cpe). at the same time, a ds1 signal is routed from the cpe to the repeater and back to the central office. when the ds1 system runs normally, i.e., when there is no loss of signal (los) or loss of frame (lof) detected in the line, no alarm will be generated. s ometimes, intermittent outburst of electrical noise s on the line might result in bipolar violation or bit errors in the incoming signals, but these errors in general w ill not trigger the equipment to generate alarms. they will at most trigger the framer to generate interrupts which wo uld cause the local microprocessor to interrupt as well as add statistics in the performance monitoring ac cumulator registers. now, consider a case in which the ds1 line from the repeater to cpe is broken or interrupted, resultin g in a complete loss of incoming data or a severely impair ed signal quality. upon detection of loss of signal (los) or loss of frame (lof) condition, the cpe will generat e an internal red alarm, also known as the service alarm indication. this alarm will normally trigger a micr oprocessor interrupt informing the user that an inc oming signal failure is happening. when the cpe is in the red alarm state, it will tra nsmit the yellow alarm to the repeater indicating t he loss of an incoming signal or loss of frame synchronization . this yellow alarm informs the repeater that there is a f igure 103. s imple d iagram of ds1 s ystem m odel ds1 receive framer block ds1 transmit framer block ds1 receive framer block ds1 transmit framer block ds1 transmit section ds1 transmit section ds1 receive section ds1 receive section co repeater cpe simple ds1 system model
xrt86l30 240 rev. 1.0.1 single t1/e1/j1 framer/liu combo problem further down the line and its transmission is not being received at the cpe. the figure below illustrates the scenario in which the ds1 connectio n from the repeater to cpe is broken. the repeater, upon detection of yellow alarm origin ated from the cpe, will transmit a blue alarm, also known as alarm indication signal (ais) to the co. blue al arm is an all ones pattern indicating that the equi pment is functioning but unable to offer service due to fail ures originated from remote side. it is sent such t hat the equipment downstream will not lose clock synchroniz ation even though no meaningful data is received. t he f igure 104. g eneration of y ellow a larm by the cpe upon detection of line failure ds1 receive framer block ds1 transmit framer block ds1 receive framer block ds1 transmit framer block ds1 transmit section ds1 transmit section ds1 receive section ds1 receive section co repeater cpe the ds1 line is broken cpe declares red alarm internally yellow alarm
xrt86l30 241 single t1/e1/j1 framer/liu combo rev. 1.0.1 figure below illustrates this scenario in which th e repeater is sending an ais to co upon detection o f yellow alarm originated from the cpe. now let us consider another scenario in which the d s1 line between co and the repeater is broken. agai n, upon detection of loss of signal (los) or loss of f rame (lof) condition, the repeater will generate an internal red alarm. this alarm will normally trigge r a microprocessor interrupt informing the user tha t an incoming signal failure is happening. the repeater will also send an all ones ais pattern downstream to the cpe and a yellow alarm back to t he co. the cpe uses the ais signal to recover received clock and remain in synchronization with the syste m. upon detecting the incoming ais signal, the cpe wil l generate a yellow alarm to the repeater to indica te the f igure 105. g eneration of ais by the r epeater upon detection of y ellow a larm originated by the cpe ds1 receive framer block ds1 transmit framer block ds1 receive framer block ds1 transmit framer block ds1 transmit section ds1 transmit section ds1 receive section ds1 receive section co repeater cpe the ds1 line is broken cpe declares red alarm internally yellow alarm repeater detects yellow alarm and generate ais to co ais
xrt86l30 242 rev. 1.0.1 single t1/e1/j1 framer/liu combo loss of incoming signal. the figure below illustrat es this scenario in which the repeater is sending a n ais to the cpe and the cpe is sending a yellow alarm back to the repeater. 12.6.1 how to configure the framer to transmit ais as we discussed in the previous section, alarm indi cation signal (ais) or blue alarm is transmitted by the intermediate node to indicate that the equipment is still functioning but unable to offer services. it is an all ones (except for framing bits) pattern which can be used by the equipment further down the line to maintain clock recovery and timing synchronization. the xrt86l30 framer can generate two types of ais: framed ais unframed ais unframed ais is an all ones pattern. if unframed ai s is sent, the equipment further down the line will be able to maintain timing synchronization and be able to reco ver clock from the received ais signal. however, du e to the lack of framing bits, the equipment farther down th e line will not be able to maintain frame synchroni zation and will declare loss of frame (lof). on the other hand, the payload portion of a framed ais pattern is all ones. however, a framed ais patt ern still has correct framing bits. therefore, the equipment further down the line can still maintain frame synchronization as well as timing synchronization. in this case, no lof or red alarm will be declared. f igure 106. g eneration of y ellow a larm by the cpe upon detection of ais originated by the r epeater ds1 receive framer block ds1 transmit framer block ds1 receive framer block ds1 transmit framer block ds1 transmit section ds1 transmit section ds1 receive section ds1 receive section co repeater cpe the ds1 line is broken repeater declares red alarm internally yellow alarm repeater detects yellow alarm and generate ais to co ais
xrt86l30 243 single t1/e1/j1 framer/liu combo rev. 1.0.1 the transmit alarm indication signal select bits of the alarm generation register (agr) enable the two types of ais transmission that are supported by the xrt86 l30 framer. the table below shows configurations of the transmit alarm indication signal select bits of the alarm generation register (agr). 12.6.2 how to configure the framer to generate red a larm upon detection of loss of signal (los) or loss of f rame (lof) condition, the repeater will generate an internal red alarm when enabled. this alarm will no rmally trigger a microprocessor interrupt informing the user that an incoming signal failure is happening. the loss of frame declaration enable bit of the ala rm generation register (agr) enables the generation of red alarm. the table below shows configurations of the of frame declaration enable bit of the alarm generation register (agr). 12.6.3 how to configure the framer to transmit yello w alarm upon detection of loss of signal (los) or loss of f rame (lof) condition, the receiver will transmit th e yellow alarm back to the source indicating the loss of an incoming signal. this yellow alarm informs the sour ce that there is a problem further down the line and its tr ansmission is not being received at the destination . the xrt86l30 framer supports transmission of yellow alarm when running at the following framing format s: sf mode esf mode n mode t1dm mode yellow alarm is transmitted in different forms for various framing formats. the yellow alarm generatio n select bits of the alarm generation register (agr) enable transmission of different types of yellow alarm tha t are supported by the xrt86l30 framer. alarm generation register (agr)(address = 0x0108h) b it n umber b it n ame b it t ype b it d escription 3-2 transmit ais select r/w these read/write bit-fields allows the user to c hoose which one of the two ais pattern supported by the xrt86l30 framer wi ll be transmitted. 00 - no ais alarm is generated. 01 - enable unframed ais alarm of all ones pattern. 10 - enable framed ais alarm of all ones pattern ex cept for framing bits. 11 - no ais alarm is generated. alarm generation register (agr)(address = 0x0108h) b it n umber b it n ame b it t ype b it d escription 6 loss of frame declaration enable r/w this read/write bit-field permits the framer to declare red alarm in case of loss of frame alignment (lof). when receiver module of the framer detects loss of frame alignment in the incoming data stream, it will generate a red al arm. the framer will also generate an rxlofs interrupt to notify the mic roprocessor that an lof condition is occurred. a yellow alarm is then r eturned to the remote transmitter to report that the local receiver detec ts lof. 0 - red alarm declaration is disabled. 1 - red alarm declaration is enabled.
xrt86l30 244 rev. 1.0.1 single t1/e1/j1 framer/liu combo 12.6.4 transmit yellow alarm in sf mode in sf mode, the xrt86l30 supports transmission of y ellow alarm in two ways. when the yellow alarm generation select bits of the alarm generation regi ster are set to 01 or 11, the second msb of all ds0 channels is transmitted as zero. this is yellow ala rm for ds1 standard. when the yellow alarm generation select bits of the alarm generation register are set to 10, the frami ng bit of frame 12 is transmitted as one. this is yellow a larm for j1 standard. 12.6.5 transmit yellow alarm in esf mode in esf mode, the xrt86l30 transmits yellow alarm on the 4kbit/s data link channel. the facility data l ink bits are sent in the pattern of eight ones followed by eight zeros. the number of repetitions of this pattern depends on the duration of yellow alarm generation select bits of the alarm generation register. when these select bits are set to 01 or 11, the following scen ario will happen: 1. if bit 0 of yellow alarm generation select forms a pulse width shorter or equal to the time required t o trans- mit 255 patterns on the 4kbit/s data link, the alar m is transmitted for 255 patterns. 2. if bit 0 of yellow alarm generation select forms a pulse width longer than the time required to transm it 255 patterns on the 4kbit/s data link, the alarm contin ues until bit 0 goes low. 3. a second pulse on bit 0 of yellow alarm generation select during an alarm transmission resets the patt ern counter. the framer will send another 255 patterns of the yellow alarm. n ote : to pulse bit 0, this bit must be programmed to 1 and then reset back to 0. the pulse width is the duration in time that this bit remains at 1. when these select bits are set to 10, bit 1 of the yellow alarm generation select forms a pulse that c ontrols the duration of yellow alarm transmission. the alarm co ntinues until bit 1 goes low. when these select bits are set to 01, the following scenario will happen: 1. if bit 0 of yellow alarm generation select forms a pulse width shorter or equal to the time required t o trans- mit 255 patterns on the 4kbit/s data link, the alar m is transmitted for 255 patterns. 2. if bit 0 of yellow alarm generation select forms a pulse width longer than the time required to transm it 255 patterns on the 4kbit/s data link, the alarm contin ues until bit 0 goes low. 3. a second pulse on bit 0 of yellow alarm generation select during an alarm transmission resets the patt ern counter. the framer will send another 255 patterns of the yellow alarm. 12.6.6 transmit yellow alarm in n mode in n mode, when the yellow alarm generation select bits of the alarm generation register are set to 01 , 10 or 11, the second msb of all ds0 channels is transmitt ed as zero. 12.6.7 transmit yellow alarm in t1dm mode in t1dm mode, when the yellow alarm generation sele ct bits of the alarm generation register are set to 01, 10 or 11, the yellow alarm bit (the third lsb of ti meslot 23) is set to zero.the table below shows con figurations of the yellow alarm generation select bits of the a larm generation register (agr).
xrt86l30 245 single t1/e1/j1 framer/liu combo rev. 1.0.1 ) alarm generation register (agr)(address = 0x0108h) b it n umber b it n ame b it t ype b it d escription 5-4 yellow alarm generation select r/w 00 - transmission of yellow alarm is disabled. 01 - the framer transmits yellow alarm by convertin g the second msb of all outgoing twenty-four ds0 channel into zero. 10 - the framer transmits yellow alarm by sending t he super-frame align- ment bit (fs) of frame 12 as one. 11 - the framer transmits yellow alarm by convertin g the second msb of all outgoing twenty-four ds0 channel into zero. n mode: 00 - transmission of yellow alarm is disabled. 01, 10 or 11 - the framer transmits yellow alarm by converting the second msb of all outgoing twenty-four ds0 channel into ze ro. esf mode: when the framer is in esf mode, it transmits yellow alarm pattern of eight ones followed by eight zeros (1111_1111_0000_0000) through the 4kbit/s data link bits. 00 - transmission of yellow alarm is disabled. 01 - the following scenario will happen: 1. if bit 0 of yellow alarm generation select forms a pulse width shorter or equal to the time required to transmit 2 55 patterns on the 4kbit/s data link, the alarm is transmitted for 255 patterns. 2. if bit 0 of yellow alarm generation select forms a pulse width longer than the time required to transmit 255 patte rns on the 4kbit/s data link, the alarm continues until bit 0 goes low . 3. a second pulse on bit 0 of yellow alarm generation select during an alarm transmission resets the pattern counter. t he framer will send another 255 patterns of the yellow alarm. 10 - bit 1 of the yellow alarm generation select fo rms a pulse that controls the duration of yellow alarm transmission. the alar m continues until bit 1 goes low. 11 - the following scenario will happen: 1. if bit 0 of yellow alarm generation select forms a pulse width shorter or equal to the time required to transmit 2 55 patterns on the 4kbit/s data link, the alarm is transmitted for 255 patterns. 2. if bit 0 of yellow alarm generation select forms a pulse width longer than the time required to transmit 255 patte rns on the 4kbit/s data link, the alarm continues until bit 0 goes low . 3. a second pulse on bit 0 of yellow alarm generation select during an alarm transmission resets the pattern counter. t he framer will send another 255 patterns of the yellow alarm. t1dm mode: 00 - transmission of yellow alarm is disabled. 01, 10 or 11 - the framer transmits yellow alarm by setting the yellow alarm bit (y-bit) to zero.
xrt86l30 246 rev. 1.0.1 single t1/e1/j1 framer/liu combo
xrt86l30 247 single t1/e1/j1 framer/liu combo rev. 1.0.1 13.0 performance monitoring (pmon) the function of performance monitoring is designed to accumulate error events like line code (bipolar) violations, parity errors, frame alignment errors, etc. using saturating counters. when an accumulati on interval is signaled by a one-second interrupt (if enabled), the current counter value can be accessed by the microprocessor. after a read by the microprocessor , the counters are reset and begin accumulating err or events for the next interval. the counters are res et in such a manner that error events during the re set period are not missed. 13.1 receive line code violation counter (16-bit) a line code violation is any event of pulses that d oes not comply with b8zs or hdb3 encoding standards . line code violations and bi-polar violations cause the l cv counter to increment if this feature is enabled. the msb is stored in register 0x0900h and the lsb is stored in register 0x0901h. 13.2 16-bit receive frame alignment error counter (1 6-bit) a framing bit error event is defined as a error pat tern found in fas or bit 2 of the non-fas. this co unter is disabled during loss of frame synchronization condi tions. it is not disabled during loss of synchroni zation at either the cas or crc-4 multiframe stage. the msb is stored in register 0x0902h and the lsb is stored in register 0x0903h. 13.3 receive severely errored frame counter (8-bit) a severely errored frame event is defined as the oc currence of two consecutive errored frame alignment signals that are not responsible for loss of frame alignment. the contents of this register are store d in 0x0904h. 13.4 receive crc-6/4 block error counter (16-bit) a synchronization bit error event is defined as a c rc-6/4 error received. the counter is disabled dur ing loss of sync at either the frame/fas or esf/crc4 level, but it will not be disabled if loss of multiframe sync occurs at the cas level. the msb is stored in register 0x090 5h and the lsb is stored in register 0x0906h. 13.5 receive far-end block error counter (16-bit) 13.6 receive slip counter (8-bit) a slip event is defined as a replication or deletio n of a t1/e1 frame by the receiving slip buffer. t he contents of this register are stored in 0x0909h. 13.7 receive loss of frame counter (8-bit) a lofc is a count of the number of times a loss of fas frame has been declared. this parameter provid es the capability to measure an accumulation of short failure events. the contents of this register are stored in 0x090ah. 13.8 receive change of frame alignment counter (8-bi t) a cofa is declared when the newly-locked framing is different from the one offered by off-line framer. the contents of this register are stored in 0x090bh. 13.9 frame check sequence error counters 1, 2, and 3 (8-bit each) these counters accumulate the times of occurrence t he receive frame check sequence error is detected b y the lapd controllers. the contents for lapd 1 are stor ed in register 0x090ch. the contents for lapd 2 ar e stored in register 0x091ch. the contents for lapd 3 are stored in register 0x092ch. 13.10 prbs error counter (16-bit) this counter contains the 16-bit prbs bit error eve nt. the msb is stored in register 0x090dh and the lsb is stored in register 0x090eh. 13.11 transmit slip counter (8-bit) a slip event is defined as a replication or deletio n of a t1/e1 frame by the transmit slip buffer. th e contents of this register are stored in 0x090fh.
xrt86l30 248 rev. 1.0.1 single t1/e1/j1 framer/liu combo 13.12 excessive zero violation counter (16-bit) this register contains the accumulation of the even ts in which excessive zeros have occurred. this is defined as more than 3-bit for hdb3, more than 7-bits for b 8zs, and more than 15-bits for ami. the msb is sto red in register 0x0910h and the lsb is stored in register 0x0911h.
xrt86l30 249 single t1/e1/j1 framer/liu combo rev. 1.0.1 14.0 appendix a: ds-1/e1 framing formats 14.1 the e1 framing structure a single e1 frame consists of 256 bits which is cre ated 8000 times per second. this yields a bit-rate of 2.048mbps. the 256 bits within each e1 frame are g rouped into 32 octets or timeslots. these timeslots are numbered from 0 to 31. each timeslot is 8 bits in length and is transmitted most significant bit fir st, numbered bit 0. figure 107 presents a diagram of a single e1 frame. not all of these timeslots are available to transmi t voice or user data. for instance, timeslot 0 is a lways reserved for system use and timeslot 16 is sometimes used (reser ved) by the system. hence, within each e1 frame, e ither 30 or 31 of the 32 timeslots are available for transpo rting user or voice data. in general, there are tw o types of e1 frames, fas and non-fas. in any e1 data stream, th e e1 frame begins with a fas frame followed by non- fas frame and then alternates between the two. 14.1.1 fas frame timeslot 0 within the fas e1 frame contains a frami ng alignment pattern and therefore supports framing . the bit-format of timeslot 0 is presented in table 175 . the si bit within the fas e1 frame typically car ries the results of a crc-4 calculation. the fixed framing pattern (e.g., 0, 0, 1, 1, 0, 1, 1) will be used by the receive e1 framer at the remote terminal for frame synchron ization/alignment purposes. f igure 107. s ingle e1 f rame d iagram t able 175: b it f ormat of t imeslot 0 octet within a fas e1 f rame b it 0 1 2 3 4 5 6 7 value si 0 0 1 1 0 1 1 function international bit frame alignment signaling (fas) pattern description- operation in practice, the si bit within the fas e1 frame car ries the results of a crc-4 calculation, which is discussed in greater detail in section 14.2.1. the fixed framing pattern (e.g., 0, 0, 1, 1, 0, 1, 1) is used by the receive e1 framer at the remote terminal for frame synchronization/alignment purposes. timeslot 0 timeslot 1 timeslot 29 0 1 2 3 4 5 6 7 timeslot 30 timeslot 31 e1 frame
xrt86l30 250 rev. 1.0.1 single t1/e1/j1 framer/liu combo 14.1.2 non-fas frame timeslot 0 within the non-fas e1 frame contains bit s that support signaling or data link message trans mission. the bit-format of timeslot 0 is presented in table 176 . the si bit in the non-fas frame typically carrie s a specific value that will be used by the receive e1 framer for crc multi-frame alignment purposes. t able 176: b it f ormat of t imeslot 0 octet within a n on -fas e1 f rame b it 0 1 2 3 4 5 6 7 value si 1 a sa4 sa5 sa6 sa7 sa8 function6 international bit fixed value yellow alarm na tional bits description- operation international bit the si bit within the non- fas e1 frame typically carries a specific value that will be used by the receive e1 framer for crc multi-frame align- ment purposes. fixed at 1 bit-field 1 contains a fixed value 1. this bit- field will be used for fas framing synchroni- zation/alignment pur- poses by the remote receive e1 framer. fas frame yellow alarm bit this bit-field is used to transmit a yellow alarm to the remote terminal. this bit-field is set to 0 during normal conditions, and is set to 1 whenever the receive e1 framer detects an los (loss of signal) or lof (loss of framing) condition in the incoming e1 frame data. national bits these bit-fields can be used to carry data link information from the local transmitting terminal to the remote receiving ter- minal. since the national bits only exist in the non- fas frames, they offer a maximum signaling data link bandwidth of 20kbps.
xrt86l30 251 single t1/e1/j1 framer/liu combo rev. 1.0.1 14.2 the e1 multi-frame structure there are two types of e1 multi-frame structures, c rc multi-frame and cas multi-frame. the cas multi- frame can be considered a subset of the crc multi-f rame, in that cas is an option to carry signaling information within the crc multi-frame structure. 14.2.1 the crc multi-frame structure a crc multi-frame consists of 16 consecutive e1 fra mes, with the first of these frames being a fas fra me. from a frame alignment point of view, timeslot 0 of each of these e1 frames within the multi-frame are the most important 16 octets. table 177 presents the bit-format for all timeslot 0 octets within a 16 frame crc multi-frame. the crc multi-frame is divided into 2 sub multi-fra mes. sub-multi-frame 1 is designated as smf1 and s ub- multi-frame 2 is designated as smf2. smf1 and smf2 each consist of 8 e1 frames having 4 fas frames an d 4 non-fas frames. there are two interesting things to note in table 177 . first, all of the bit-field 0 positions within each of the fas frames (within each smf) are designated as c1, c2, c3 and c4. these four bit-f ields contain the crc-4 values which have been computed o ver the previous smf. hence, while the transmit e1 framer is assembling a given smf, it computes the c rc-4 value for that smf and inserts these results i nto the c1 through c4 bit-fields within the very next smf. these crc-4 values ultimately are used by the remo te receive e1 framer for error detection purposes. n ote : this framing structure is referred to as a crc mult i-frame because it permits the remote receiving ter minal to locate and verify the crc-4 bit-fields. the second interesting thing to note regarding table 177 is that the bit-field 0 positions within each of t he non- fas frames (within the entire mf) are of a fixed 6- bit pattern 0, 0, 1, 0, 1, 1 along with two bits, e ach designated as e. this 6-bit pattern is referred to as the crc multi-frame alignment pattern, which can t able 177: b it f ormat of all t imeslot 0 octets within a crc m ulti - frame smf f rame n umber b it 0 b it 1 b it 2 b it 3 b it 4 b it 5 b it 6 b it 7 1 0 c1 0 0 1 1 0 1 1 1 0 1 a sa4 sa5 sa6 sa7 sa8 2 c2 0 0 1 1 0 1 1 3 0 1 a sa4 sa5 sa6 sa7 sa8 4 c3 0 0 1 1 0 1 1 5 1 1 a sa4 sa5 sa6 sa7 sa8 6 c4 0 0 1 1 0 1 1 7 0 1 a sa4 sa5 sa6 sa7 sa8 2 8 c1 0 0 1 1 0 1 1 9 1 1 a sa4 sa5 sa6 sa7 sa8 10 c2 0 0 1 1 0 1 1 11 1 1 a sa4 sa5 sa6 sa7 sa8 12 c3 0 0 1 1 0 1 1 13 e 1 a sa4 sa5 sa6 sa7 sa8 14 c4 0 0 1 1 0 1 1 15 e 1 a sa4 sa5 sa6 sa7 sa8
xrt86l30 252 rev. 1.0.1 single t1/e1/j1 framer/liu combo ultimately be used by the remote receive e1 framer for crc multi-frame synchronization/alignment. th e "e" bits are used to indicate that the local receiv e e1 framer has detected errored sub-multi-frames.
xrt86l30 253 single t1/e1/j1 framer/liu combo rev. 1.0.1 14.2.2 cas multi-frames and channel associated signa ling cas multi-frames are only relevant if the user is u sing cas or channel associated signaling. if the u ser is implementing common channel signaling then the cas multi-frame is not available. 14.2.2.1 channel associated signaling if the user operates an e1 channel in channel assoc iated signaling, then timeslot 16 octets within eac h e1 frame will be reserved for signaling. such signali ng would convey information such as on-hook, off-ho ok conditions, call set-up, control, etc. in cas, thi s type of signaling data that is associated with a particular voice channel will be carried within timeslot 16 of a par ticular e1 frame within a cas multi-frame. the cas is carried in a multi-frame structure which consists o f 16 consecutive e1 frames. the framing/byte format of a cas multi-frame is presented in figure 108 . timeslot 16 within frame 0 is a special octet that is used to convey cas multi-frame alignment informa tion, and to convey multi-frame alarm information to the remote terminal. the bit-format of timeslot 16 wit hin frame 0 of a cas multi-frame is 0000 xyxx. the upp er nibble of this octet contains all zeros and is u sed to identify itself as the cas multi-frame alignment si gnal. if cas is used, then the user is advised to insure that none of the other timeslot 16 octets contain the va lue "0000". the lower nibble of this octet contains the expression "xyxx". the x-bits are the spare bits a nd should be set to "0" if not used. the y-bit is used to indicate a multi-frame alarm condition to the remot e terminal. during normal operation, this bit-fiel d is cleared to "0". however, if the local receive e1 fr amer detects a problem with the incoming multi-fram es, then the local transmit e1 framer will set this bit -field within the next outbound cas multi-frame to "1". n ote : the local transmit e1 framer will continue to set t he y-bit to "1" for the duration that the local rec eive e1 framer detects this problem. timeslot 16 within frame 1 of the cas multi-frame c ontains 4 bits of signaling data for voice channel 1 and 4 bits of signaling data for voice channel 17. times lot 16 within frame 2 contains 4 bits of signaling data for voice channel 2 and 4 bits of signaling data for vo ice channel 18, and this continues for all e1 frame s. f igure 108. f rame /b yte f ormat of the cas m ulti -f rame s tructure frame 0 frame 1 frame 2 frame 15 0000 xyxx timeslot 16 timeslot 16 timeslot 16 timeslot 16 abcd abcd signaling data associated with timeslot 1 signaling data associated with timeslot 17 abcd abcd abcd abcd cas multiframe alignment pattern x = dummy bits y = carries the multiframe yellow alarm bit signaling data associated with timeslot 2 signaling data associated with timeslot 18 signaling data associated with timeslot 15 signaling data associated with timeslot 31 a single cas multiframe
xrt86l30 254 rev. 1.0.1 single t1/e1/j1 framer/liu combo 14.2.2.2 common channel signaling (ccs) common channel signaling is an alternative form of signaling from cas. in ccs, whatever signaling dat a which is transported via the outbound e1 data strea m, carries information that applies to all of the v oice channels as a set (e.g., timeslots 1 through 15 and 17 through 31) in the e1 frame. there are numerous other variations of common channel signaling that are ava ilable. some of these are listed below. 31 voice channels with the common channel signaling being transported via the national bits. 30 voice channels with the common channel signaling data being transported via the national bits and c as data being transported via timeslot 16. 30 voice channels with the common channel signaling being processed via timeslot 16. (e.g., primary ra te isdn signaling). f igure 109. e1 f rame f ormat fr 0 fr 1 fr 2 fr 3 fr 4 fr 5 fr 6 fr 15 fr 14 fr 13 fr 12 fr 11 fr 10 fr 9 fr 8 fr 7 1 n n n n n a 1 a d c b a d c b 0 7 6 5 4 3 2 1 1 1 1 0 1 1 0 0 0 x x y x 0 0 0 ts 0 ts 1 ts 2 ts 15 ts 31 ts 30 ts 29 ts 18 - 28 ts 17 ts 16 ts 3 - 14 fas cas time slot 16 time slot 0 time slots 1-15, 17-31 channel data b. frames 1-15 b. odd frames 1, 3, 5-15 a. even frames 0, 2, 4-14 a. frame 0 8 bits/ time slot 32 time slots/frame 16 frames/ multiframe non-fas
xrt86l30 255 single t1/e1/j1 framer/liu combo rev. 1.0.1 14.3 the ds1 framing structure a single t1 frame is 193 bits long and is transmitt ed at a frame rate of 8000hz. this results in an a ggregate bit rate of 1.544 mbit/s. basic frames are divided int o 24 timeslots numbered 1 thru 24 and a framing bit as shown in figure 110 . each timeslot is 8 bits in length and is transm itted most significant bit first, numbered bit 0. t his results in a single timeslot data rate of 8 bits x 8000/sec = 64 kbit/s. f igure 110. t1 f rame f ormat ds1 frame bit 0 0 bit 1 1 bit 2 2 bit 3 3 bit 4 4 bit 5 5 bit 6 6 bit 7 7 f-bit timeslot 1 timeslot 2 - 23 timeslot 24 timeslot 23 125 m mm m s
xrt86l30 256 rev. 1.0.1 single t1/e1/j1 framer/liu combo 14.4 t1 super frame format (sf) the superframe format (sf), is also referred to as the d4 format. the requirement for associated sign aling in frames 6 and 12 dictates that the frames be disting uishable. this leads to a multiframe structure cons isting of 12 frames per superframe (sf) as shown in figure 111 and table 178 . this structure of frames and multiframes is defined by the f-bit pattern. the f -bit is designated alternately as an ft bit (termin al framing bit) or fs bit (signalling framing bit). the ft bit car ries a pattern of alternating zeros and ones (10101 0) in odd frames that defines the boundaries so that one time slot may be distinguished from another. the fs bit carries a pattern of (001110) in even frames and defines th e multiframe boundaries so that one frame may be distinguished from another. f igure 111. t1 s uperframe pcm f ormat b a bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 8 bits per timeslot ft or fs ft or fs ts 1 ts 1 ts 2 ts 2 ------------------ ------------------ ts 13 ts 13 ------------------- ------------------- ts 24 ts 24 fr 1 fr 1 fr 2 fr 2 ------------------ ------------------ fr 7 fr 7 ------------------- ------------------- fr 11 fr 11 fr 12 fr 12 signalling information bit 7 during: frame 12 frame 6 24 timeslots per frame frame = 193 bits multiframe sf = 12 frames
xrt86l30 257 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 178: s uperframe f ormat f rame b it f-b its b it u se in e ach t imeslot s ignalling c hannel t erminal f raming f t t erminal f raming f s t raffic s ig 1 0 1 ---- 1-8 ---- ---- 2 193 ---- 0 1-8 ---- ---- 3 386 0 ---- 1-8 ---- ---- 4 579 ---- 0 1-8 ---- ---- 5 772 1 ---- 1-8 ---- ---- 6 965 ---- 1 1-7 8 a 7 1158 0 ---- 1-8 ---- ---- 8 1351 ---- 1 1-8 ---- ---- 9 1544 1 ---- 1-8 ---- ---- 10 1737 ---- 1 1-8 ---- ---- 11 1930 0 ---- 1-8 ---- ---- 12 2123 ---- 0 1-7 8 b
xrt86l30 258 rev. 1.0.1 single t1/e1/j1 framer/liu combo 14.5 t1 extended superframe format (esf) in extended superframe format (esf), as shown in figure 112 and table 179 , the multiframe structure is extended to 24 frames. the timeslot structure is i dentical to d4 (sf) format. robbed-bit signaling i s accommodated in frame 6 (a-bit), frame 12 (b-bit), frame 18 (c-bit) and frame 24 (d-bit). the f-bit pattern of esf contains three functions: 1. framing pattern sequence (fps), which defines the f rame and multiframe boundaries. 2. facility data link (fdl), which allows data such as error-performance to be passed within the t1 link. 3. cyclic redundancy check (crc), which allows error p erformance to be monitored and enhances the reli- ability of the receivers framing algorithm. f igure 112. t1 e xtended s uperframe f ormat d c crc crc fd l fd l b a bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 8 bits per timeslot fp s o r f s fps or fs ts 1 ts 1 ts 2 ts 2 ----------------- - ----------------- - ts 13 ts 13 ------------------ - ------------------ - ts 24 ts 24 fr 1 fr 1 fr 2 fr 2 ----------------- - ----------------- - fr 13 fr 13 ------------------ - ------------------ - fr 23 fr 23 fr 24 fr 24 signalling information bit 7 during: frame 24 frame 18 frame 12 frame 6 24 timeslots per frame frame = 193 bits multiframe esf = 24 frames
xrt86l30 259 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 179: e xtended s uperframe f ormat f rame b it f-b its b it u se in e ach t imeslot s ignalling c hannel fps dl crc t raffic s ig 16 4 2 1 0 ---- m ---- 1-8 ---- ---- ---- ---- 2 193 ---- ---- c1 1-8 ---- ---- ---- ---- 3 386 ---- m ---- 1-8 ---- ---- ---- ---- 4 579 0 ---- ---- 1-8 ---- ---- ---- ---- 5 772 ---- m ---- 1-8 ---- ---- ---- ---- 6 965 ---- ---- c2 1-7 8 a a a 7 1158 ---- m ---- 1-8 ---- ---- ---- ---- 8 1351 0 ---- ---- 1-8 ---- ---- ---- ---- 9 1544 ---- m ---- 1-8 ---- ---- ---- ---- 10 1737 ---- ---- c3 1-8 ---- ---- ---- ---- 11 1930 ---- m ---- 1-8 ---- ---- ---- ---- 12 2123 1 ---- ---- 1-7 8 b b a 13 2316 ---- m ---- 1-8 ---- ---- ---- ---- 14 2509 ---- ---- c4 1-8 ---- ---- ---- ---- 15 2702 ---- m ---- 1-8 ---- ---- ---- ---- 16 2895 0 ---- ---- 1-8 ---- ---- ---- ---- 17 3088 ---- m ---- 1-8 ---- ---- ---- ---- 18 3281 ---- ---- c5 1-7 8 c a a 19 3474 ---- m ---- 1-8 ---- ---- ---- ---- 20 3667 1 ---- ---- 1-8 ---- ---- ---- ---- 21 3860 ---- m ---- 1-8 ---- ---- ---- ---- 22 4053 ---- ---- c6 1-8 ---- ---- ---- ---- 23 4246 ---- m ---- 1-8 ---- ---- ---- ---- 24 4439 1 ---- ---- 1-7 8 d b a n otes : 1. fps indicates the framing pattern sequence (...00 1011...) 2. dl indicates the 4kb/s data link with message bit s m. 3. crc indicates the cyclic redundancy check with bi ts c1 to c6 4. signaling options include 16 state, 4 state and 2 state.
xrt86l30 260 rev. 1.0.1 single t1/e1/j1 framer/liu combo 14.6 t1 non-signaling frame format the non-signaling (n) framing format is a simplifie d version of the t1 super frame. the n-frame consi sts of four frames with two fs bits and two ft bits. the fs bits can be used as a proprietary 4kbps data lin k transmission. signaling is not supported in this f raming format. t able 180: n on -s ignaling f raming f ormat 14.7 t1 data multiplexed framing format (t1dm) t1dm uses a similar framing structure as the sf (d4 ), such that the fs and ft bits on the individual f rame boundaries remain the same. the differentiation be tween t1dm and sf is within the payload time slots. time slot 24 cannot be used for data when configured for t1dm. time slot 24 is dedicated for a special synchronization byte as shown in figure 113 . the y-bit is to carry the status of the yellow a larm. the r-bit is dedicated for a remote signaling bit typically not used. however, the framer allows this bit to carry an hdlc message. time slots 1 through 23 are used to carry the seven bit word from each of the 23 ds-0 signal s. f rame b it f-b its t erminal f raming f t t erminal f raming f s 1 0 1 ---- 2 193 ---- x 3 386 0 ---- 4 579 ---- x f igure 113. t1dm f rame f ormat f time slot 1 time slots 2 through 23 time slot 24 bit 1 bit 2 bit 3 bit 4 bit 6 bit 7 c bit 5 1 0 1 1 y r 0 1 12 t1dm frames per multi-frame t1dm frame
xrt86l30 261 single t1/e1/j1 framer/liu combo rev. 1.0.1 14.8 slc-96 format (slc-96) slc framing mode allows synchronization to the slc? 96 data link pattern. this pattern described in be llcore tr-tsy-000008, contains both signaling information and a framing pattern that overwrites the fs bit of the sf framer pattern. see table 181 . t able 181: slc ? 96 f s b it c ontents f rame # fs b it f rame # fs b it f rame # fs b it 2 0 26 c2 50 0 4 0 28 c3 52 m1 6 1 30 c4 54 m2 8 1 32 c5 56 m3 10 1 34 c6 58 a1 12 0 36 c7 60 a2 14 0 38 c8 62 s1 16 0 40 c9 64 s2 18 1 42 c10 66 s3 20 1 44 c11 68 s4 22 1 46 0 70 1 24 c1 48 1 72 0 n otes : 1. the slc ? 96 frame format is similar to that of sf as shown i n table 178 with the exceptions shown in this table. 2. c1 to c11 are concentrator bit fields. 3. m1 to m3 are maintenance bit fields. 4. a1 and a2 are alarm bit fields. 5. s1 to s4 are line switch bit fields. 6. the fs bits in frames 46, 48 and 70 are spoiler b it switch are used to protect against false multiframing.
xrt86l30 262 rev. 1.0.1 single t1/e1/j1 framer/liu combo electrical characteristics absolute maximums power supply....................................... .. - 0.5v to +3.465v power consumption lqfp package...... ..............726mw storage temperature ............................... -65c to 150c input logic signal voltage (any pin) .........-0.5v to + 5.5v operating temperature range.................-40c t o 85c esd protection (hbm)......................... ..................>2000v supply voltage ...................... gnd-0.5v to + vdd + 0.5v input current (any pin) ................. ..................... + 100ma dc electrical characteristics test conditions: ta = 25c, vdd = 3.3v + 5% unless otherwise specified s ymbol p arameter m in . t yp . m ax . u nits c onditions i ll data bus tri-state bus leakage current -10 +10 a v il input low voltage 0.8 v v ih input high voltage 2.0 vdd v v ol output low voltage 0.0 0.4 v i ol = -1.6ma v oh output high voltage 2.4 vdd v i oh = 40a i oc open drain output leakage current a i ih input high voltage current -10 10 a v ih = vdd i il input low voltage current -10 10 a v il = gnd t able 182: xrt86l30 p ower c onsumption vdd=3.3v5%, t a =25c, unless otherwise specified m ode s upply v oltage i mpedance termination r esistor t ransformer r atio t yp . m ax . u nit t est c onditions r eceiver t ransmitter e1 3.3v 75 w internal 1:1 1:2 695 mw prbs pattern e1 3.3v 120 w internal 1:1 1:2 726 mw prbs pattern t1 3.3v 100 w internal 1:1 1:2 660 mw prbs pattern
xrt86l30 263 single t1/e1/j1 framer/liu combo rev. 1.0.1 ac electrical characteristics transmit framer test conditions: ta = 25c, vdd = 3.3v + 5% unless otherwise specified s ymbol p arameter m in . t yp . m ax . u nits c onditions t 1 txmsync setup time (falling edge txserclk) 5 ns t 2 txmsync hold time (falling edge txserclk) 1 ns t 3 txsync setup time (falling edge txserclk) 5 ns t 4 txsync hold time (falling edge txserclk) 1 ns t 5 txser setup time (falling edge txserclk) 5 ns t 6 txser hold time (falling edge txserclk) 1 ns t 7 rising edge of txserclk to rising edge of txchclk 11 ns t 8 rising edge of txchclk to valid txchn[4:0] data 6 ns t 9 txsig setup time (falling edge txserclk) 5 ns t 10 txsig hold time (falling edge txserclk) 1 ns t 11 txfract setup time (falling edge txserclk) 5 ns t 12 txfract hold time (falling edge txserclk) 1 ns f igure 114. f ramer s ystem t ransmit t iming d iagram txmsync txserclk txser txsync txchn[4:0] (output) txchclk (output) txchn_0 (txsig) txchn_1 (txfract) t 1 t 3 t 5 t 2 t 4 t 6 t 7 t 8 t 9 t 10 t 11 t 12 a b c d
xrt86l30 264 rev. 1.0.1 single t1/e1/j1 framer/liu combo ac electrical characteristics receive framer test conditions: ta = 25c, vdd = 3.3v + 5% unless otherwise specified s ymbol p arameter m in . t yp . m ax . u nits c onditions rxserclk as an output t 13 rising edge of rxserclk to rising edge of rxcasync 4 ns t 14 rising edge of rxserclk to rising edge of rxcrcsync 4 ns t 15 rising edge of rxserclk to rising edge of rxsync 4 ns t 16 rising edge of rxserclk to rising edge of rxser 6 ns t 17 rising edge of rxserclk to rising edge of valid rxchn[4:0] data 6 ns rxserclk as an input t 18 rising edge of rxserclk to rising edge of rxcasync 9 ns t 19 rising edge of rxserclk to rising edge of rxcrcsync 9 ns t 20 rising edge of rxserclk to rising edge of rxsync 9 ns t 21 rising edge of rxserclk to rising edge of rxser 11 ns t 22 rising edge of rxserclk to rising edge of valid rxchn[4:0] data 11 ns f igure 115. f ramer s ystem r eceive t iming d iagram (r x serclk as an o utput ) rxcrcsync rxcasync rxserclk (output) rxser rxsync rxchn[4:0] t 13 t 14 t 15 t 16 t 17
xrt86l30 265 single t1/e1/j1 framer/liu combo rev. 1.0.1 f igure 116. f ramer s ystem r eceive t iming d iagram (r x serclk as an i nput ) ac electrical characteristics transmit overhead fra mer test conditions: ta = 25c, vdd = 3.3v + 5% unless otherwise specified s ymbol p arameter m in . t yp . m ax . u nits c onditions t 23 txsync setup time (falling edge txserclk) 5 ns t 24 txsync hold time (falling edge txserclk) 1 ns t 25 rising edge of txserclk to txohclk 11 ns f igure 117. f ramer s ystem t ransmit o verhead t iming d iagram rxcrcsync rxcasync rxserclk (input) rxser rxsync rxchn[4:0] t 18 t 19 t 20 t 21 t 22 txserclk txsync t 23 t 24 txohclk t 25
xrt86l30 266 rev. 1.0.1 single t1/e1/j1 framer/liu combo ac electrical characteristics receive overhead fram er test conditions: ta = 25c, vdd = 3.3v + 5% unless otherwise specified s ymbol p arameter m in . t yp . m ax . u nits c onditions rxserclk as an output t 26 rising edge of rxserclk to rising edge of rxsync 4 ns t 27 rising edge of rxserclk to rising edge of rxo- hclk 7 ns t 28 rising edge of rxserclk to rising edge of rxoh 7 ns rxserclk as an input t 29 rising edge of rxserclk to rising edge of rxsync 9 ns t 30 rising edge of rxserclk to rising edge of rxo- hclk 12 ns t 31 rising edge of rxserclk to rising edge of rxoh 12 ns f igure 118. f ramer s ystem r eceive o verhead t iming d iagram (r x serclk as an o utput ) f igure 119. f ramer s ystem r eceive o verhead t iming d iagram (r x serclk as an i nput ) rxserclk (output) rxohclk rxsync rxoh t 26 t 27 t 28 rxoh interface with rxserclk as an input rxoh t 29 t 30 t 31 rxserclk (input) rxohclk rxsync
xrt86l30 267 single t1/e1/j1 framer/liu combo rev. 1.0.1 electrical characteristics t able 183: e1 r eceiver e lectrical c haracteristics vdd=3.3v5%, t a = -40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions receiver loss of signal: number of consecutive zeros before rlos is set input signal level at rlos rlos de-asserted 15 12.5 32 20 db % ones cable attenuation @1024khz itu-g.775, etsi 300 233 receiver sensitivity (short haul with cable loss) 11 db with nominal pulse amplitude of 3.0v for 120 w and 2.37v for 75 w applica- tion. with -18db interference signal added. receiver sensitivity (long haul with cable loss) 0 43 db with nominal pulse amplitude of 3.0v for 120 w and 2.37v for 75 w applica- tion. with -18db interference signal added. input impedance 13 k w input jitter tolerance: 1 hz 10khz-100khz 37 0.2 uipp uipp itu g.823 recovered clock jitter transfer corner frequency peaking amplitude - 36 -0.5 khz db itu g.736 jitter attenuator corner fre- quency (-3db curve) (jabw=0) (jabw=1) - 10 1.5 - hz hz itu g.736 return loss: 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz 14 20 16 - - db db db itu-g.703
xrt86l30 268 rev. 1.0.1 single t1/e1/j1 framer/liu combo t able 184: t1 r eceiver e lectrical c haracteristics vdd=3.3v5%, t a =-40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions receiver loss of signal: number of consecutive zeros before rlos is set input signal level at rlos rlos clear 160 15 12.5 175 20 - 190 -- db % ones cable attenuation @772khz itu-g.775, etsi 300 233 receiver sensitivity (short haul with cable loss) 12 - db with nominal pulse amplitude of 3.0v for 100 w termination receiver sensitivity (long haul with cable loss) normal extended 00 - 36 45 db db with nominal pulse amplitude of 3.0v for 100 w termination input impedance 13 - k w jitter tolerance: 1hz 10khz - 100khz 138 0.4 -- -- uipp at&t pub 62411 recovered clock jitter transfer corner frequency peaking amplitude -- 9.8 - 0.1 khz db tr-tsy-000499 jitter attenuator corner frequency (-3db curve) - 6 -hz at&t pub 62411 return loss: 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz -- - 20 25 25 -- - db db db t able 185: e1 t ransmit r eturn l oss r equirement f requency r eturn l oss g.703/ch-ptt ets 300166 51-102khz 8db 6db 102-2048khz 14db 8db 2048-3072khz 10db 8db
xrt86l30 269 single t1/e1/j1 framer/liu combo rev. 1.0.1 t able 186: e1 t ransmitter e lectrical c haracteristics vdd=3.3v5%, t a =-40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions ami output pulse amplitude: 75 w application 120 w application 2.13 2.70 2.37 3.00 2.60 3.30 vv transformer with 1:2 ratio and 9.1 w resistor in series with each end of pri- mary. output pulse width 224 244 264 ns output pulse width ratio 0.95 - 1.05 - itu-g.703 output pulse amplitude ratio 0.95 - 1.05 - itu-g.703 jitter added by the transmitter output - 0.025 0.05 uip p broad band with jitter free tclk applied to the input. output return loss: 51khz -102khz 102khz-2048khz 2048khz-3072khz 8 14 10 -- - -- - db db db etsi 300 166, chptt t able 187: t1 t ransmitter e lectrical c haracteristics vdd=3.3v5%, t a =-40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions ami output pulse amplitude: 2.4 3.0 3.60 v use transform er with 1:2.45 ratio and measured at dsx-1 output pulse width 338 350 362 ns ansi t1.102 output pulse width imbalance - - 20 - ansi t1.102 output pulse amplitude imbalance - - + 200 mv ansi t1.102 jitter added by the transmitter output - 0.025 0.05 uip p broad band with jitter free tclk applied to the input. output return loss: 51khz -102khz 102khz-2048khz 2048khz-3072khz -- - 15 15 15 -- - db db db
xrt86l30 270 rev. 1.0.1 single t1/e1/j1 framer/liu combo f igure 120. itu g.703 p ulse t emplate t able 188: t ransmit p ulse m ask s pecification test load impedance 75 w resistive (coax) 120 w resistive (twisted pair) nominal peak voltage of a mark 2.37v 3.0v peak voltage of a space (no mark) 0 + 0.237v 0 + 0.3v nominal pulse width 244ns 244ns ratio of positive and negative pulses imbalance 0.95 to 1.05 0.95 to 1.05 10% 10% 10% 10% 10% 10% 269 ns (244 + 25) 194 ns (244 C 50) 244 ns 219 ns (244 C 25) 488 ns (244 + 244) 0% 50% 20% v = 100% nominal pulse note C v corresponds to the nominal peak value. 20% 20%
xrt86l30 271 single t1/e1/j1 framer/liu combo rev. 1.0.1 f igure 121. dsx-1 p ulse t emplate ( normalized amplitude ) t able 189: dsx1 i nterface i solated pulse mask and corner points m inimum curve m aximum curve t ime (ui) n ormalized amplitude t ime (ui) n ormalized amplitude -0.77 -.05v -0.77 .05v -0.23 -.05v -0.39 .05v -0.23 0.5v -0.27 .8v -0.15 0.95v -0.27 1.15v 0.0 0.95v -0.12 1.15v 0.15 0.9v 0.0 1.05v 0.23 0.5v 0.27 1.05v 0.23 -0.45v 0.35 -0.07v 0.46 -0.45v 0.93 0.05v 0.66 -0.2v 1.16 0.05v 0.93 -0.05v 1.16 -0.05v t able 190: ac e lectrical c haracteristics vdd=3.3v5%, t a =25c, unless otherwise specified p arameter s ymbol m in . t yp . m ax . u nits mclkin clock duty cycle 40 - 60 % mclkin clock tolerance - 50 - ppm
xrt86l30 272 rev. 1.0.1 single t1/e1/j1 framer/liu combo ordering information package dimensions p art # p ackage o perating temperature r ange XRT86L30IV 128 pin lqfp(14x20x1.4mm) -40 c to +85 c e b 1 38 39 64 65 102 103 128 a 2 a a 1 a aa a l c e1 e d d1 note: the control dimensions are the millimeter col umn min max 0.0551 max min 0.8740 0.0079 0.0106 0.0571 0.0059 1.60 1.40 0.0630 0.7835 0.8583 0.0035 0.0067 0.0531 0.0020 0.27 1.45 19.90 21.80 0.09 0.17 1.35 0.15 0.05 0.7913 0.0295 0.5551 0.6378 0.0177 0.0197 bsc 0.5472 0.6220 20.10 22.20 0.20 0.50 bsc 14.10 13.90 16.20 15.80 0.75 millimeters 0.45 0 o 7 o 0 o 7 o symbol d1 d c b a2 a1 a inches l e e1 e a
273 notice exar corporation reserves the right to make changes to the products contained in this publication in o rder to improve design, performance or reliability. exar co rporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representa tion that the circuits are free of patent infringement. chart s and schedules contained here in are only for illu stration purposes and may vary depending upon a users speci fic application. while the information in this publ ication has been carefully checked; no responsibility, howe ver, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonabl y be expected to cause failure of the life support system or to significantly affect its safety or effectiveness . products are not authorized for use in such appli cations unless exar corporation receives, in writing, assurances t o its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks ; (c) potential liability of exar corporation is ad equately protected under the circumstances. copyright 2008 exar corporation datasheet january 2008. reproduction, in part or whole, without the prior w ritten consent of exar corporation is prohibited. xrt86l30 rev. 1.0.1 single t1/e1/j1 framer/liu combo revision history r evision # d ate d escription 1.0.0 03/06/07 new logo, removed preliminary for rele ase to production. changed ti/e1.403- 1955 to t1/e1.403. changed table 170, signaling cha nnel 4 from abcb to abab and 2 from abaa to aaaa corrected rxlos_n pin desc ription. this pin will be tri-stated not pulled "low" when the framer or liu is not declaring the los defect condition. 1.0.1 01/07/08 changed package information from ib to iv, and tqfp to lqfp.

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